University of Florida Infrared Astrophysics Group

1
Flamingos-2Electronics Design Overview
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Electronics Design Presentation Summary

• Section 1 Detector Status
• Section 2
• Electronics Requirements
• Section 3
• System Overview Design Implementation

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Section 1Detector Availability and Delivery

• Detectors available presently at UF
• Flamingos 1 Bare Mux
• Flamingos 1 Engineering Detector
• Science Detector Delivery
• Procured and delivered by Gemini
• Needed by Feb of 2004

4
Detector Anomalies Issues

• Cross Talk
• The Flamingos-1 Science detector sees a form of
  cross talk that has not been seen by others.
  This takes the form of a residual image to the
  left and right of the channel with the real
  image. It needs to be noted that this was NOT
  seen in the engineering array and by all other
  testing indications, it is NOT in the external
  analog electronics.

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Detector Anomalies Issues

• Well DepthIt was found that the Flamingos-1
  detector has a well depth of about 250e3
  electrons not the 100e3 as noted in the spec
  sheets. This is not to far fetched as the
  integrating capacitance has a posted variability
  of about a factor of 2.This does effect the
  noise and preamp requirements. For F-1 we mapped
  275,000e- to 55,000 counts. That gives a
  conversion gain of about 5 e-/ADU.If we were to
  map the linear ( lt1.0 ) range of about 100,000
  that yields morel like 1.8e- / ADU. This is much
  more compatible with the noise expected from the
  system of about 2.0 ADU.It is probable that a
  scientifically driven choice will have to be made
  regarding what is determined to be the useful
  well depth. ( Linear vs. Saturated )

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Section 2 Electronics Design Requirements

• ( Summary )
• Read out HAWAII-2 Array at maximum pixel rate.(
  Flamingos-1 data shows this to be about 1.3 Sec /
  frame )
• Clock digitize the array in such a manner so as
  not to significantly degrade the intrinsic
  detector read noise.
• Transport the co-added and buffered data to the
  ICS

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Data System Noise Contribution
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Required Array Readout Rates

• The array is limited to about 1.3 seconds / Frame
  in the 32 output mode while using an external
  3216 analog mux.\
• This gives a total pixel rate of about 3.2 Mpix /
  sec
• The electronics system is capable of between 16
  and 48 Mpix / sec depending on the ADC converters
  used. The FLAMINGOS-2 system will use 1.0 Mhz
  converters and thus yield about 16.0 Mpix / sec.
  Clearly exceeding the array requirements.

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Section 3Electronics System Overview
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Main Component Break Down

• Array Sequencer Processor ( ASP) Rack Components
• Instrument Control System ( ICS ) Rack
  Components
• Temperature / Vacuum Monitor Control
• Motor Control

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Overall Electronics Block Diagram
EPICS CannelAccess LAN
DHS LAN
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Dewar Mounted Electronic Modules

• Bias Generator / Clock Driver
• Provides array DC voltages
• Sets clock rail voltages.
• Converts TTL inputs to clock level output
• Fanout Board
• No active electronics, only passive filtering
• Preamps
• 32 channels of low noise amplification.
• Mux down to 16 channels for the electronic system
  inputs.
• Digital to Analog Converter ( DAC ) controlled
  offsets.

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Bias Clock Module Features

• Programmable Clock Bias Voltage Levels ( 8 bit
  ).
• Programmed via ASP ( Array Sequencer Preprocessor
  ) CPU commands
• Voltage levels and Clock Phases are TTL Inputs.
• All Inputs are Opto-Isolated to eliminate ground
  loops.
• Module has dedicated power supply also to
  eliminate ground loop paths.
• Will use replication of existing Flamingos-1 Bias
  board.

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Dewar Modules ( Bias / Clock Diagram )
15
In Dewar Electronics Diagram
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Preamp Description

• Two Stage Preamp with 3216 Mux
• Gain Bandwidth Product (GBW) available in current
  configuration 170 Mhz.
• Pixel Rates expected ( ( (2048)2 / 1.3 sec/16
  channels ) gt 202 kHz )
• Band Width ( BW ) needed at pixel rates rates
  expected for 16 bit settling 460 kHz.
• Hawaii-2 Preamp Gain required 5
• Gain Bandwidth needed is only 2.3 Mhz
• Programmable offsets are provided. - Probably
  set once and forget.

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Dewar Modules ( Preamp )
Analog Outputs from Array
Analog Outputs to ASP Rack
Second Stage Preamp
First Stage Preamp
16
16
21 Mux
TTL Offset Control from ASP
Preamp Power
Offset DAC
Opto - Isolators
16
Analog Ground Plane
18
Overall Electronics Block Diagram
EPICS CannelAccess LAN
DHS LAN
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ASP Rack Contents

• Array Signal Processor Main MCE-4 Contents
• VME CPU ( MC 68020 based )
• Pattern Generator Board ( PGB )
• ADC / Coadder Board(s) (ADC )
• Optical Fiber and Aux. I/O ( UFB )
• Preamp / Bias Main Analog Linear Supplies

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ASP Physical Layout
VME CPU
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Pattern Generator Board

• Identical to existing OSCIR, Flamingos TRECS
  units.
• Simple RAM based clocking patterns.
• Clock Phases available 24
• Internal clocks 8
• Clocking resolutions to 50 ns at highest frame
  rates.
• Will drive arrays to 250ns / pixel.
• Pattern Ram depth up to 512K words.
• All logic is Xilinx FPGA based.

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PGB Block Diagram
23
ASP Physical Layout
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ADC / Coadder Boards

• 1.0, 2.0 or 3.0 MHz, 16 bit Converters
• Coadders
• Word depth to 32 bits per pixel
• One Coadder per channel.
• On Board Data Buffers isolate average data rates
  from peak image data rates.
• Analog section Opto-Isolated from Digital
  portions to eliminate ground loops through the
  digital system.
• ADC Boards Individually Analog Powered to
  eliminate ground loops through the analog power
  supply commons.

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ADC Board Block Diagram
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ASP Physical Layout
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Upper Fiber Board

• Data input path is 128 bits wide
• Relatively slow 10 MHz synchronous data clock
• Serves as mother board for Gatir Remote Camera
  Interface (GRCI) Fiber Module
• Three opto isolated RS-232 ports for aux..
  Control functions.
• Not used with Flamingos - 2
• Opto-isolated TTL I/O port ( 8 bit in / 8 bit out
  )
• Not used with Flamingos - 2

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Upper Fiber Board Block Diagram
Input Data Registers
Science Data Bus 128 bit
Science Data32 bit
32
Mux. Control
Handshake Control
Science Data Command ControlFiber Link
Clock Drivers
Clocks10 Mc.20 Mc.
VME Bus
Backplane
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GRCI Module Description Features

• Semi-Custom module designed by EDT( Engineering
  Design Team ) .
• Supports direct 32 bit parallel input.
• Supports data rates as high as 25 M samples/sec
  (100MB/sec)
• Direct technical support and warrantee supplied
  by original manufacturer at no additional cost.
• Custom features are mechanical only. Electronic
  features are identical with EDTs standard
  product, leveraging experience and increasing
  reliability .

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Grounding Issues Topics

• Entire structure will be safety Earth grounded
  for safety.
• The analog data system single point ground will
  be at the preamp ground plane in that module.
  All other portions of the data system are
  referenced through this point.
• All analog modules are powered with separate
  power supplies.
• Bias Pod, Preamp Pod each ADC Board
• Clock Bias TTL input lines are opto-isolated at
  the input of the Clock / BIAS module.
• The analog outputs of the preamps are isolated
  from the remainder of the data system by
  opto-isolators after the ADCs.
• Each ADC board is also powered with a dedicated
  supply.

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Grounding Diagram
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Science Data Path
Fiber Aux.. TTL I/O Board
ICS Rack
Fiber Link
Rackmount Spark-2
Temperature Monitor Vacuum Monitor
DHS LAN Connection
Motor Drivers Supply
PPC board may replace main CPU in slot 1
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Temperature Monitor Control

• The cold bench will be thermally controlled at
  two points for thermal stability and monitored at
  several other points as needed.
• A Lakeshore 332 will be used for control as it
  has two control channels. One _at_50 Watts, one _at_10
  Watts.
• A Lakeshore 218 will be used for all other
  temperature monitoring.

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Temperature Monitor Points
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Pressure Monitor(s)

• A Pfeiffer TPG262 controller and two Pfeiffer
  PKR251 sensors will be used with
  Flamingos-2.These will monitor pressure in both
  the camera as well as the MOS dewars.
• The 262 allows for up to two sensor inputs and
  is RS-232 interfaced.

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Motion Control

• Flamingos-2 will use the same IMS-483 indexers
  that were used with TRECS.
• The TRECS motor indexer chassis has all the
  indexers on a daisy chain. While this is
  functional, it was a problem at times in
  diagnosing any problems that may arise on the
  communication channel(s).
• Therefore, on FLAMINGOS-2, the indexers will NOT
  be daisy chained via RS-485. Instead, each
  indexer will be individually controlled from the
  Pearl-e Terminal Server via RS-232.

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Bar Code Reader

• The MOS plates for FLAMINGOS will be bar coded.
• At this time a reader has not been selected.
• Issues
• Mounting of a reader within the confines of the
  MOS dewar.
• Possible Cryogenic operation or survival.
• Bar Tag adhesion at cryogenic temperatures.
• Tagging of slot positions as well as MOS plates.
• Tag Generation

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Grounding Issues Topics

• Entire structure will be safety Earth grounded
  for safety.
• The analog data system single point ground will
  be at the preamp ground plane in that module.
  All other portions of the data system are
  referenced through this point.
• All analog modules are powered with separate
  power supplies.
• Bias Pod, Preamp Pod each ADC Board
• Clock Bias TTL input lines are opto-isolated at
  the input of the Clock / BIAS module.
• The analog outputs of the preamps are isolated
  from the remainder of the data system by
  opto-isolators after the ADCs.
• Each ADC board is also powered with a dedicated
  supply.

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Top Level System Cable DiagramVISIO -
Flamingos-2 Preliminary
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Individual Cable Diagram Example
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Areas of Risk

• 1) System Read Noise
• 2) Excess Low Frequency Noise
• 3) Bar Code Reader issues
• 4) Timely Construction
• 5) Parts Procurement Spares

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Areas of Risk

• 1) System Read Noise
• F-1 had read noises in excess of those found in
  other instruments.
• This was due primarily to the scaling of the
  system to 275,000 e- instead of 100,000 as most
  others are.
• Resolved by Rescaling to the 100K linear portion
  of the integration curve.
• Risk LOW

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Areas of Risk

• 3) Bar Code Reader
• These have been enumerated in a previous slide.
• Resolution
• See what others have done.
• Buy one and play with it. ( cheap 600 )
• Do it early!
• Risk if addressed soon Low if we
  wait Medium

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Areas of Risk

• 2) Excess Low Frequency Noise
• F-1 had 50-60 Hz pickup wich varied from site to
  site.
• This was comprised oc two components. A) long
  single ended cables from the preamp to the ASP
  rack and b) long single ended cables from the
  array to the preamp inside the dewar.
• Resolution a) F-2 will be using differential
  signals from the preamp to the ADCs in the ASP
  rack. This was shown to lower the 50-60 hz noise
  in TRECS both in the lab and on site. It should
  be noted that the TRECS noise levels showed no
  change when installed on the telescope.
• Resolution b) F-2 will have a MUCH shorter path
  from the array to the preamps. In F-1 the length
  was about 1 to 1.5 meters while the length for
  F-2 will be about .3 meters.
• Risk Low

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Areas of Risk

• 4) Timely Construction Delivery July 2004 is
  the schedule for most of the electronics SW IT
  to begin. There are two main issues here a)
  MCE-4 construction b) System cable
  construction.
• Resolution
• a) MCE-4 is a copy of at least three other
  systems of identical design. This should be a
  strait construction project with good
  manufacturing documentationRisk Low
• b) If the cable definitions are ready to go in
  January 2004, then construction of all needed
  cables should not be a problem for two FTEs
  devoted to the task of construction and final
  documentation.RISK Low

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Areas of Risk

• 5) Parts Procurement Spares
• Parts are becoming harder and harder to locate.
• Currently identified problem parts include the
  Xilinx chips, and memory simm modules.
• Resolution
• An advanced purchase of these critical components
  has been made and have been received.
• If spares are desired, they should be considered
  in the VERY near future.
• Risks Program Delivery Low -gt Medium
  Spares Medium -gt High

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Appendix Item ListingsSupport Materials supplied
on CDor at CDR

• A CDR Board Level Schematics
• B CD Individual Cable Diagram(s) example
• C CD Overall Cable Map
• D CD Various Excel Preamp Calculations
• E CDR Recommended Spares Listing
• F CD Lakeshore and Pfeiffer Manuals