The CMU Reconfigurable Computing Project

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The CMU Reconfigurable Computing Project

• April 9, 1999
• Mihai Budiu
• mihaib_at_cs.cmu.edu

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Current Project Members
ECE Department Herman Schmit Srihari
Cadambi Matt Moe Robert Taylor Ronald Laufer
CS Department Seth Copen Goldstein Mihai Budiu
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Why Study Reconfigurable Hardware?

• It is a nice computation paradigm
• (wire your own computer)

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Why Study Reconfigurable Hardware
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Commercial Players
Source In-stat April 1998  Does not include
software, hardwire or support EPROMs
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What Is Reconfigurable Hardware?
Interconnection network
Universal gates and/or storage elements
Switches
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Basic Ingredient RAM cell
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Basic Ingredients (ctd)
0
1
1
1
A switch is controlled by a 1-bit RAM cell
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Outline

• What is reconfigurable hardware
• RH vs other computation paradigms
• Challenges in RH research
• PipeRench the CMU project
• the hardware
• the software
• Conclusions

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RH vs ASICs

• Generally Application-Specific Integrated
  Circuits will be faster than RH
• RH wires are slow big
• RH bit-slices are costly to interconnect
• RH devices must store configuration on the chip
• but
• RH can be reprogrammed
• new algorithms
• to fix bugs
• RH cheaper in small production
• RH tolerates faults better
• RH sometimes faster with staged computation

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RH vs Microprocessors

• RH less flexible (like a VLIW with fixed
  instructions)
• but
• RH provides more (customized) computation
  elements
• RH can decrease memory traffic
• RH can be tailored for specific algorithms and
  data types
• RH will not replace mP, but complement them

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Types of RH

• FPGAs bit-level logic functionality
• (the basic processing elements compute on 1 bit)
• word-based architectures PipeRench (CMU)
• (basic PE operates on 8 bits)
• (basic PE is a small ALU)
• coarse architectures RAW (MIT)
• (basic PE is a MIPS 2000 core)

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RH In A System
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Challenges In RC

• Software tools
• Programming RC like software development
• Automatic compilation from HLL
• Automatic program partitioning
• Mapping efficiently algorithms (no ISA)
• System issues
• interfaces
• find ideal RC fabric

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The CMU Reconfigurable Computing Project
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Hardware Goals

• To build a complete reconfigurable hardware
  device
• To build the system integration hardware
• To host the device in a PC

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Our Device

• Word processing elements
• Pipelined architecture
• Virtualized hardware
• Local interconnection network
• Wide pipelined bus

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Configuration memory
Data Config controller
Stripes
Processing elements
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Hardware Virtualization
Actual available hardware
Instructions currently in hardware
Program
Instructions paged out
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Hardware Virtualization (2)
Page out
compute
compute
Program in configuration memory
compute
configure
Page in
hardware
Overlap configuration with computation.
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Processing Elements
a
b
Cin
PE2
PE0
PE1
out

• Look-up table
• Any 3-to-1 function

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The Interconnection Network
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The PCI Board
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Our Target Applications
v9
Input data

• Pipelineable applications
• Stream processing (e.g. DSP, encryption)
• Multimedia processing
• Vector processing
• Limited data dependencies

v8
v7
v6
v5
HW
v4
v3
v2
Output data
v1
Computational power stems from massive parallelism
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Software Goal

• To program reconfigurable devices using the
  standard software development processes
• Compile C or Java
• Do it quickly

Java
Partitioner
Data-flow Intermediate Language
DIL
Built
Configuration
CPU
Reconfigurable HW
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Building Circuits From DIL

• a b c d
• e c - d
• variables wires
• operators gates

d
c
b


-
a
e
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Mapping Circuits To
a
b
c
a

b
c
c
a
b
-

-

-
c
a
b
-

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The DIL Compiler Front-End
Circuit
Parser Evaluator Loader
Dil input file
Backend
Loader
component library
Component circuits
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The DIL Compiler Backend
Circuit (expanded)
Circuit (placed)
Circuit
Optimizer
Placer- Router
Front-end
The whole compilation process is very fast
(compared to classical CAD tools). We can
compile two orders of magnitude faster.
Code generator
Asm
C
C
xfig
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Processing Element Size Tradeoffs
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Stripe Width Tradeoffs
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Bus Width Tradeoffs
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Clock Speed Tradeoffs(run-time)
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Project Status

• Operational
• Behavioral and structural models of Piperench in
  Verilog
• Assembler, simulator
• Tools for visualization and debugging
• One tile fabricated and tested
• Very fast compiler from intermediate language
• In work
• Prototype PipeRench to be taped this summer
• PCI board to host PipeRench in a PC

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Simulated Speed-up vs. UltraSparc _at_ 300Mhz
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Future Work

• Build the PCI board
• Build the OS device drivers
• Start investigating HLL issues
• automatic partitioning
• translation to DIL
• special code transformations

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Conclusions

• A set of important applications can benefit from
  RC devices
• RC offer potential for substantial performance
  improvement at a low cost
• RC devices will soon be mainstreamin the
  embedded computing world perhaps in the future
  they will also permeate the desktop

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