Monolithic Silicon Pixel Detectors in SOI Technology

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Monolithic Silicon Pixel Detectors in SOI
Technology
J. Marczewski, K. Domanski, P. Grabiec, M.
Grodner, K. Kucharski, B. Jaroszewicz, A.
Kociubinski, D. Tomaszewski Institute of Electron
Technology, Warszawa W. Kucewicz, S. Kuta, H.
Niemiec, M. Sapor University of Mining and
Metallurgy, Krakow M. Caccia University of
Insubria, Como Presented by Jacek Marczewski
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Outline

• SUCIMA project
• SOI imager motivation and concept
• SOI imager technology development
• Test structures and preliminary measurements
• Future tasks

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SUCIMA Silicon Ultra fast Cameras for electron
and gamma sources In Medical Applications
COMPETITIVE AND SUSTAINABLE GROWTH

• SUCIMA is a project approved by the EC within
  GROWTH, one of the lines of the Fifth Framework
  Program
• The project started off on November 1st, 2001
  and it is supposed to last for 36 months.

The collaboration is made out of 9 Dept.s or
Research Centers and 2 companies from 5 EU
countries.
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Review of SUCIMA objectives

• The main goal of the project is the
• DEVELOPMENT OF AN ADVANCED IMAGING TECHNIQUE
  OF EXTENDED RADIOACTIVE SOURCES USED IN MEDICAL
  APPLICATIONS
• where imaging has be intended as the record of
  a dose map
• Development boundary conditions are defined by
  the specific end-user requirements
• Brachytherapy
• Real-time monitor of a proton beam for
  radiotherapic treatments

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• The specific task of the SUCIMA project is the
• DEVELOPMENT OF A SOI IMAGER
• Why SOI?
• fast
• sensitive
• radiation hard

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SOI Monolithic Detector Motivation

• Advantages of SOI monolithic detectors
• SOI imager as a monolithic device allows to
  reduce total sensor thickness
• Performance and radiation tolerance of readout
  electronics may benefit from reduction of active
  silicon thickness
• SOI solution allows the use of high resistive
  detector substrates

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SOI Imager Main Concept

• Detector ? handle wafer
• High resistive
• 300 ?m thick
• Electronics ? active layer
• Low resistive
• 1.5 ?m thick

Detector conventional p-n, DC-coupled Electronic
s CMOS technology on the SOI substrate
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SOI Imager Technology Development

• Technology of SOI detectors
• Integration of pixel manufacturing technique
• with typical CMOS poly-Si gate technology
• Challenges
• Fabrication of circuits at both sides of BOX
  layer
• Cross-talk between read-out electronics and
  detector
• Reliable electrical connection through BOX
• Optimization of high temperature processing

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SOI Imager Technology Development

• Technological sequence ? over 100 processes

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SOI Imager Technology Development
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Test Structures
The test structures serve as a tool for SOI
technology and layout design development. They
will be fabricated by the IET, Warsaw by the end
of the year
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An Example of Technological Test Structure
The test structure for checking treshold voltage
differences for close situated transistors
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An Example of Design Test Structure The test
structure for F-E concept evaluation
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Preliminary measurements
The bulk test structures has been used to produce
SOI transistors on SOITEC wafers. The technology
sequence was similar as it is provided for SOI
detectors. The substrate parameters are exactly
the same like for future SOI detectors except low
resistivity of the handle wafers.
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Preliminary measurements
The CMOS transistors on thin substrate (SOI) have
different doping profiles than the bulk ones.
Parameters of well implantation were changed to
get Vth0.7/-0.2V at reasonable VBR (? 19 V)
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TASKS FOR THE NEAR FUTURE

• Production of test structures (next 2 months)
• Extraction of device parameters (Jan/Feb 03)
• Technology development (3 runs expected)
• Preliminary verification of design (mid-year 2003)

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INSTITUTE of ELECTRON TECHNOLOGY

AL. Lotników 32/46 02-668 Warszawa POLAND
http//www.ite.waw.pl jmarcz_at_ite.waw.pl