A Guide to ALTERA Tool

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A Guide to ALTERA Tool
Silicon Micro SystemsBangalore
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Now the next slides will help you to write a VHDL
Code compile it,do Simulation.
Also you will come across Following Features of
ALTERA MAX plus II
Floorplan EditorCompilerSimulatorTiming
AnalyserProgrammer
Graphical EditorSymbol EditorText
EditorWaveform EditorText Editor
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Steps to work on Altera Max II

• Create your directory in explorer e.g.
  D\SiMS
• Open Max Plus II from the ICON in the Desktop

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Keep in Mind !
This is comment window
Follow the window with this colour to proceed
your design
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ALTERA Max plus II Main Tool Window
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File -gtProject-gtName
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VLSI
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Write the Project Name e.g.VLSI
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Your project VLSI is created in your specified
directory(SiMS)
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Now We will Create a Text Editor
File -gt New
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Select Text Editor file Radio Button -gt Ok
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Copy the below code to Text editor
library IEEE use IEEE.std_logic_1164.allentity
and_2 iS port ( a in STD_LOGIC
b in STD_LOGIC c out STD_LOGIC
) end and_2architecture and_2_arch of and_2
is begin c lta and b end and_2_arch
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The code is copied in Text Editor
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Now we will have to save the code
File -gtSave
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Note Your Entity Name file name should be
samewith extension (.vhd)
Give the file name e.g. and_2.vhd -gt Ok
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Reserved words will be highlighted after saving
the file
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Now we will set the project to current file
File -gtProject -gtSet Project To Current File
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During compilation the design will be compiled
implemented to the default device in one execution
MAXplus -gt Compiler
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Design Flow Window
Click Start
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Error Message Window
Ok
Close the Compilation Window
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Select The waveform Editor for simulation
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waveform Editor
Now We will simulate the design using waveform
Editor
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Simulation Window
Right Click Here Select The Nodes From SNF
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Select The Nodes From SNF
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a,b are input c is output node
List -gt gt
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Ok
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File -gt Save
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File name will be Entity name by default
Ok
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We will apply the Stimulus value to the node from
the menu bar
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We will apply predefined clock to node a
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Ready For Simulation
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MAX plus -gt Simulator
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Timing Simulation by default
Start
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Your Simulation is successful
Ok
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Result of your design
Close the waveform Editor
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Floorplan Editor
Now we will see the Floorplan Editor
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View Of Your Design in Selected Device
MAX plus II Floorplan Editor
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Click on to see the Floor Plan Editor
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Floorplan View
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Floorplan View
Layout -gt Device View
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Down Loading
Now We will Down Load the program to the device
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Down Loading the code to the device
You need to connect hardware board
MAX plus II -gt Programmer
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Converting the code to symbolic Editor
Open your current VHDL Code File -gtOpen
-gtand_2.vhd -gtOk
Assign -gt Convert Absolute Assignment Format- gtOk
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Click On Start -gtOk -gt Close The Compilation
Window
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Select The Radio Button Symbol Editor file
File -gt Open -gtand_2.spm
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Symbol Editor Of Your Code
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Graphical /Schematic Editor
Follow the steps given in slides 4-9
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Choose Radio Button Graphical Editor file
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Double Click On the Page
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You will get this page
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Write the symbol name e.g. and2 -gt Ok
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You will get AND gate symbol with 2 inputs
Now we will take Buffers to connect ports of AND
gate. Write input -gt Ok
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Copy the Input Buffer paste it .Double click on
the page -gt output -gt Ok
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Now you have got all the buffers
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Now we will join the pads with the ports
F3
Click F3 to select the line type.Drag from input
pads to the port of AND gate as shown
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Completed Graphical view of AND gate
Note No .of pads no of Inputs No. of Outputs
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Save the Graphical Editor File.
File -gtSave
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Give the file name e.g. and2.gdf
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AND Gate view after saving with .gdf extension
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Give Port name (a,b,c)by double clicking on the
pad. File -gt save
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Set the the project to current file
File -gt Project -gt Set Project to Current file
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Compile the file.
Maxplus II -gt Compiler
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In the mid way of compilation of current file.
Click on Start
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File has been compiled.
After compilation click -gt OK
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You have complied the design.If you wanted to see
the VHDL code for the same .Then follow the steps
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Max plus II -gt Compiler
Interface -gt VHDL Netlist Writer
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VHDL Netlist Writer is Added
Click On Start
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You will get the VHDL Netlist generated file
and2.vho
Double Click on VHDL Netlist Writer (.vho)
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