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The Microprocessor and

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communicates with and controls the operation of other ... MDRout,IRin. 3. Zout,PCin, WMFC. 2. PCout,MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin ... – PowerPoint PPT presentation

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Title: The Microprocessor and


1
Tutorial 11
  • The Microprocessor and
  • its Architecture

2
Objectives
  • Revision on lecture note(CPU Architecture)
  • Intel x86

3
CPU
  • What is CPU?
  • one central unit that executes program
    instructions
  • communicates with and controls the operation of
    other subsystems within the computer
  • its main function to fetch and execute
    instructions

4
CPU
5
CPU Fundamental
  • As you know, fetching and execution are broken
    down into smaller steps(e.g. movement between
    registers, addition by using ALU, etc)
  • Each of these smaller steps is a machine code,
    i.e. an assembly instruction
  • Assembly program will be assembled to machine
    instructions and then put in the main memory (You
    should know that already, Right?)

6
CPU Fundamental
  • Depends on the machine instruction, the CPU will
    generate a set of control signals to control
    other subsystem
  • (You also known that)
  • CPU bus(What is bus?)
  • The bus is internal to the CPU
  • connected the components in the CPU
  • (e.g. ALU, GPR, MAR, MDR, PC, )

7
CPU
Memory Function Completion indicates the
operation in memory is completed
CPU with Single-bus
CPU internal bus
From control unit
To main memory
Y,Z and TEMP are registers. That are transparent
to programmers. CPU will use it by itself.
From control unit
8
Example of Bus organization
  • Fetch a Word from MM
  • Assume the address of the memory location to be
    accessed is in R1 and the memory data are to be
    loaded into R2
  • Write a Word to MM

CPU idle
9
Control signals
  • To MM
  • Read, Write, Reset, etc
  • To Registers
  • Riin input data to Ri from CPU bus if 1
  • Riout output data in Ri to CPU bus if 1
  • 0 bus is used by others
  • reset, etc
  • To ALU
  • Add, Sub, Mul, Div, etc

10
Example of Control Signals
  • Add data in R1 and R2 registers and
  • put the result to R3

Electronic switch In control 1 will get input
else will not Out control 1 will output the
data else 0 will not
11
1-bit register with Switch
Z means the tri-state is in high impedance mode
Control to SR latch
SR latch (God! What is it?)
12
Control Sequence
  • ADD A,R1

Fetch
Execution
13
Control Sequence
  • BRN(conditional/unconditional)

For step 4, if not satisfy branch condition, then
End branch address PC Offset
14
CPU with 3 internal buses
  • required significantly fewer control steps
  • ADD R1,R2,R3 (one clock cycle)
  • execution phase to be performed in one
  • clock cycle
  • Y is not required because ALU can take two
  • inputs from two registers from two data buses
  • Z is not required because ALU can write the
  • result to the destination register by 3rd bus
  • performs register-to-register operations in
  • a single clock cycle

15
CPU Architecture
16
Control Signal
  • But how to generate the control signals as the
    control sequence discussed before?
  • By microprogramming
  • What is microprogramming?
  • Using a sequence of microinstructions to
    generates a sequence of control signals

17
Microprogramming
  • A control word(CW) is a word whose individual
    bits represent the various control signals
  • Each CW represents a set of control signals in
    one step of control sequence of an instruction,
    which is called microinstruction
  • A sequence of CWs, which is referring to the
    control sequence of a machine instruction, is
    called microroutine
  • Microprogram memory contains the microroutine of
    all instructions
  • Depends on IR, a starting address of
    corresponding microroutine is given to
    microprogram counter
  • MicroPC will be incremented and then a sequence
    of CWs will be given out

18
Hand-shaking with Memory
  • In the control sequence, there are steps that
    have to wait for MFC from memory. A signal WMFC
    is used.

19
Hand-shaking with Memory
  • Why MR?
  • if
  • But, if it starts at (i1)-th pulse,
  • However, after the drop of (i1)-th pulse and
  • before the raise of (i2)-th pulse,
  • It is wrong!

20
80x86
21
8086 (Review)
  • 16-bit processor with 20-bit address bus
  • Direct mode addressing with memory space of
    1MByte
  • 14 words by 16-bit register set
  • (You should be familiar with them)
  • Byte addressable
  • For address and data operands, the least
    significant byte of the word is stored in the
    lower valued address location and the most
    significant byte in the next higher address
    location

22
8086 (Review)
23
8086
  • Why there is no Program Counter(PC)?
  • How to indicate the next instruction to be
    executed?
  • How stack works?
  • What is the function of SP?
  • What is the starting position of SP?
  • How CALL works?
  • How to jump to other procedure?
  • How to return(RET) to previous procedure?
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