XTRP Review

1
XTRP Review

• Agenda
• Introduction/Overview K. Pitts 10
• Board Status M. Kasten 25
• DAQ/Interface/Test Software N. Eddy 15
• Map Generation/Implementation H. Kim 15
• Schedule/Summary Pitts/Kasten
• XTRP Group
• Nathan Eddy, Lee Holloway, Mike Kasten,
• Hyunsoo Kim, Kevin Pitts
• Documentation http//web.hep.uiuc.edu/Engin/CDF/
  XTRP/

2
People Involved

• Mike Kasten
• lead engineer board design/fab/testing
• Nathan Eddy
• postdoc DAQ/testing software, Java-man
• Hyunsoo Kim
• postdoc map generation/implementation interface
  with database and front end offline simulation
• Kevin Pitts
• spiritual guidance Spirit? Maybe. Guidance? Not
  much. Knowledge? None.
• Plan to add a grad student very soon

3
Trigger

• XTRP is the interface between tracks in the COT
  (XFT) and the remainder of the Level 1 trigger.
• XFT data input to the XTRP
• Output info to
• L1 calorimeter (extrapolate)
• L1 muon (extrapolate)
• Track Trigger (pass)
• Global L1 L2 (pass)
• SVT (pass)

4
XTRP Overview

• XTRP system
• 1 clock/control board
• 1 clock/control transition module
• 12 data boards
• 12 data board transition modules
• Entire system one VME crate
• VIPA-style (not CDF-style)
• P2 not bussed
• location 2nd floor trigger room

5
XTRP System
6
XTRP Boards

• Clock/control board (1)
• from CDF clock, generates four phases of 132ns
  clock
• also generates 33ns clock
• controls SYNC, RESET, HOLD
• puts all ECL on backplane
• Clock/control board transition module
• SVT, PreFRED, and L2 I/O through this board
• Data board transition module (12)
• receives track data from XFT
• drives info out to Muon,Cal,etc.
• all XFT,CAL,MUON I/O through this board

7
XTRP Data Board

• One board per two 15o wedges
• 12 boards total (2 XFT linkers -gt 1 XTRP data
  board)
• on board two wedges denoted A and B
• Functionality
• latch XFT data every 33ns
• demux and pipe (FPGA) also buffer for L1,L2
• lookup RAMs
• handle duplicate tracks
• drive data out to CAL and Muon

8
Recent History
9
Test Setup (WH 14)

• XTRP crate
• test clock
• XTRP clock/control board
• data board
• data board transition module
• XFT linker crate
• 2 XFT linkers
• XFT linker tester
• data blaster/buffer board

Clock/control board
Data board
10
Today

• Mike Kasten
• board status
• tests, test results
• plans
• Nathan Eddy
• test and readout software package
• Hyunsoo Kim
• map generation
• download software

11
Schedule
12
Manpower

• Current
• Kasten 100, Eddy 75, Kim 100
• Future
• Kim will play a larger roll in hardware when maps
  are done
• add at least one grad student soon
• Track Trigger
• Kasten, Pitts, student
• more UIUC engineering support if needed
• Mike Haney largely done with CLEO-III trigger
• also get an EE grad student