Shobana Padmanabhan, Dan Legorreta, Moshe Looks

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Application Performance throughHardware
Acceleration

• Shobana Padmanabhan, Dan Legorreta, Moshe Looks
• CSE 560
• Oct 2005

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Application Performance
Architecture
Compiler
Algorithm
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Liquid architecture platform
FPX
Clustering application
LEON
001010 110110 001110

• LEON - SPARC8 compatible
• Open soft core

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Application runtime
Slow! Where is time spent?
FPX
LEON
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Function
Time / Cycles
Cache Hits / Misses
Read
Write
.text
main
findMatch
Can profile all aspects of micro-architecture
addQuery
computeKey
computeBase
coreLoop
fillQuery
Rnd
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Cycle-accurate profiling for free
Request Timings
FPX
findMatch 500ms coreLoop 300ms
LEON
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Improve application performance

• By reconfiguring the processor
• By creating special hardware instructions

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Reconfigure architecture
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Special hardware instruction
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Special hardware instruction
001010 110110 001110
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Related work

• Gaisler Research. http//www.gaisler.com
• Lesley Shannon and Paul Chow. Using
  reconfigurability to achieve real-time profiling
  for hardware/software codesign. In Proc. ACM
  Intl Symp. on Field Programmable Gate Arrays,
  pages 190199, 2004.
• T. Vinod Kumar Gupta, Roberto E. Ko, and Rajeev
  Barua. Compiler-directed customization of ASIP
  cores. In Proc. of the 10th Intl Symp. on
  Hardware/Software Codesign, pages 97102, May
  2002.
• Shobana Padmanabhan, Phillip Jones, et. al.
  Extracting and Improving Microarchitecture
  Performance on Reconfigurable Architectures. In
  Workshop on Compilers and Tools for Constrained
  Embedded Systems workshop at Inter. Conference on
  Compilers, Architecture, and Synthesis for
  Embedded Systems (CASES), Washington DC, Sep
  2004.
• Stretch, Inc. http//www.stretchinc.com.
• Tensilica, Inc. http//www.tensilica.com.
• John W. Lockwood. The Fieldprogrammable Port
  Extender (FPX). http//www.arl.wustl.edu/arl/proje
  cts/fpx/, December 2003.
• Paolo Ienne Kubilay Atasu, Laura Pozzi. Automatic
  application-specific instruction-set extensions
  under microarchitectural constraints. Intl Symp.
  on Field Programmable Gate Arrays, pages 190199,
  2004.
• Michael Gschwind. Instruction set selection for
  ASIP design. In Proc. of the 7th Intl Symp. on
  Hardware/Software Codesign, pages 711, May 1999.
• N. Clark, W. Tang, S. Mahlke. Automatically
  Generating Custom Instruction Set Extensions.
  Workshop on Application Specific Processors. Nov
  2002, Istanbul, Turkey.
• A. K. Verma, K. Atasu, M. Vuletic, L. Pozzi, P.
  Ienne. Automatic Application-Specific
  Instruction-Set Extensions under
  Microarchitectural Constraints. Nov 2002,
  Istanbul, Turkey.
• Kenshu Seto, Kojima Yoshihisa, Masahiro Fujita.
  Compiler Techniques for Field Modifiable
  Architectures. In Workshop on Compilers and Tools
  for Constrained Embedded Systems workshop at
  Inter. Conference on Compilers, Architecture, and
  Synthesis for Embedded Systems (CASES),
  Washington DC, Sep 2004.

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Related work cntd.

• Hierarchical Clustering in Hardware - Papers1.
  Transformation Algorithms for Data StreamsJohn W.
  Lockwood, Stephen G. Eick, Doyle J. Weishar, Ron
  Loui, James Moscola, Chip Kastner, Andrew Levine,
  Mike Attighttp//www.arl.wustl.edu/lockwood/publi
  cations/WashU-AERO_2005-AFE_Summer_Experiment_Pape
  r.pdf2.
• Implementation of a Content-Scanning Module for
  an Internet FirewallJames Moscola, John Lockwood,
  Ronald P. Loui, Michael Pachoshttp//www.arl.wustl
  .edu/projects/fpx/references/FCCM03/wu-content_sca
  nning_firewall-FCCM_03-paper.pdf3.
• FPsed A Streaming Content Search-and-Replace
  Module for an Internet FirewallJames Moscola,
  Michael Pachos, John Lockwood, Ronald P.
  Louihttp//www.arl.wustl.edu/lockwood/publication
  s/hoti11_fpsed.pdf4.
• Methods and Architectures for Realizing Fast
  Phylogenetic ComputationEngines Using VLSI Array
  Based LogicJames P. Davis, Sreesa Akella, Peter
  Waddellhttp//www.cse.sc.edu/jimdavis/Research/Pa
  pers-PDF/Bioinformatics02-Davis-Akella-Waddell5B1
  5D.pdf5.
• FPGA Implementation of Hierarchical Clustering
  AlgorithmsNiamat, M.Y., Bitter, D., Jamali,
  M.M.http//ieeexplore.ieee.org/iel4/5627/15118/006
  94410.pdf?arnumber6944106.
• Parallel Algorithms for Hierarchical
  ClusteringClark F. Olsonhttp//citeseer.ist.psu.ed
  u/olson95parallel.html7.
• Digital VLSI for Neural NetworksDan
  Hammerstromhttp//www.cecs.pdx.edu/strom/papers/h
  ammerstrom_draft2.pdf8.
• Simulation of paleocortex performs hierarchical
  clusteringJ Ambros-Ingerson, R Granger, G
  Lynchhttp//www.jstor.org/view/00368075/di002048/0
  0p0487f/0originsfx3Asfx9.
• Algorithmic Transformations in the Implementation
  ofK-means Clustering on Reconfigurable
  HardwareMike Estlick, Miriam Leeser, James
  Theiler, John J. Szymanskihttp//delivery.acm.org/
  10.1145/370000/360311/p103-estlick.pdf?key1360311
  key24848397211collGUIDEdlACMCFID54014978C
  FTOKEN8441184810.
• Design Issues for Hardware Implementation of an
  Algorithm for Segmenting Hyperspectral Imagery
  James Theiler, Miriam Leeser, Michael Estlick,
  and John J. Szymanskihttp//mrfrench.lanl.gov/jt/
  Papers/kmeans-spie-00.ps11.
• FPGA Implementation of a Network of Neuronlike
  Adaptive Elements Andres Perez-Uribe and Eduardo
  Sanchezhttp//lslwww.epfl.ch/aperez/ps/PerezSanch
  ez_icann97.ps.gz12.
• A Phylogenetic, Ontogenetic, and Epigenetic View
  of Bio-Inspired Hardware SystemsMoshe Sipper,
  Eduardo Sanchez, Daniel Mange,Marco Tomassini,
  Andres Perez-Uribe, and Andre Staufferhttp//www.c
  s.virginia.edu/bio/Sipper_POEmodel_97.pdf

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Plan
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Reconfigurable architecture
Pentium
FPGA
Custom