Junction Delineation of Axially-doped SiNWs

1
Junction Delineation of Axially-doped SiNWs
Interfaces in Si/Si1-xGex Axial NW
Heterostructures
Semiconductor Nanowire Electronics
Nanoscale field-effect device synthesis,
integration, modeling and characterization
Tsung-ta Ho, Aaron Vallett, Rebeca Diaz, Raseong
Kim, Sharis Minassian, Bangzhi Liu, Trevor Clark,
Chad Eichfeld and Nick Dellas Faculty
collaborators Elizabeth Dickey (MatSE), Suzanne
Mohney (MatSE), Joan Redwing (MatSE-EE), Mark
Lundstrom (ECE), Theresa Mayer (EE) The
Pennsylvania State University, University Park,
PA and Purdue University, West Lafayette, IN,
USA
Motivation
Current Focus
Nanoscale Device Modeling

• Interest in silicon nanowire field-effect
  transistors (SiNW FET) for continued scaling of
  logic devices into the sub-20-nm regime
• Typically fabricated using silicon-on-insulator
  top-down fabrication
• Growing interest in bottom-up assembly methods
  using nanotubes and nanowires
• Potential NW FET advantages
• Formation of wrap-around gate structures with
  reduced short-channel effects
• Fabrication of ultra-small diameter (3 nm) SiNWs
  by vapor-liquid-solid (VLS) growth is possible
  (Wu et al., Nano Lett. (2004))
• Improved transport predicted in 1D wires (Sakai,
  Jpn. J. Appl. Phys. (1980))
• In-situ doping for vertical nanowire-based MOSFET
  devices
  

• Top-gated n-channel MOSFETs using 50 nm diameter
  axially-doped n-p--n SiNWs
• Inversion-mode operation of SiNW FETs
• Improved device properties compared with
  uniformly-doped SiNW FETs
• Collect statistically significant data to extract
  effective electron mobility from devices with
  different channel lengths
• Developing p-channel MOSFET using axially-doped
  p-n--p SiNWs
• Investigate hole transport properties in inverted
  p-channel
• Demonstration of complementary-MOS (CMOS) devices
• Small diameter silicon nanowire

• Inversion-mode SiNW MOSFETs of significant
  interest for understanding the scaling effect of
  carrier transport in sub-10nm nanowire diameter
• Different scattering phenomena 2DEG inversion to
  volume inversion
• Size-dependent behavior anticipated in
  inversion-mode NW FETs

• 1D or quasi-1D transport in nanowire-based
  MOSFETs
• Subband splittings due to quantum confinement
• One or only a few subbands occupied
• Steps in IDS vs. VGS (spikes in transconductance,
  gm vs. VGS) for low VDS at low temperature
• Simulation with top-of-the-barrier ballistic
  transport model

K. H. Cho et al., IEDM 2006.
Possible nanowire-based structures with reduced
channel width
Silicon Nanowire Field-Effect Devices
Vapor-Liquid-Solid (VLS) Growth
Thermal Oxidation of SiNWs

p-
n

Au tip
n

• Studied thermal oxidation of SiNWs and impact on
  properties/devices
• Oxide properties
• Breakdown Field gt 8MV/cm
• Interface Density 3.71012 cm-2eV-1
• Addition of trichloroethane (TCA) enhances
  oxidation rate and improves Si/SiO2 interface and
  oxide quality

TEM Characterization
Selective Plating of Gold
Our studies focus on fundamental issues of
crystal growth and diameter-dependent effects in
the VLS growth of Si nanowires and axial
composition (Si1-xGex/Si) and dopant (n-p-n,
p-n-p) modulated structures.
Diameter-dependent Effects in VLS Growth of SiGe
Radial profile

• Gold particles are selectively deposited onto the
  n segments of the nanowire
• Use a 2-step plating process to selectively
  deposit and thicken gold coating.
• Gold coating can be easily identified in FESEM

• Single crystal structure with 2nm thick native
  oxide on SiNW surface
• n segments have slightly larger diameter and
  increased surface roughness

Tg425oC Si-rich
Axial profile
Axially-doped Wrap Around Gate SiNW FETs
(Inversion-mode Operation)

• Top-gated FET structure using thermally-oxidized
  axially-doped n-p--n SiNW
• Improved device properties compared with
  uniformly-doped SiNW FETs
• On/Off ratio 107, On-state current 3 µA _at_ VGS
  3 V
• Subthreshold slope 250 mV/dec
• Transconductance 1.3 µS
• Drain induced barrier lowering (DIBL) lt 50mV/V
• Effective mobility may be estimated from channel
  resistance
• Rtotal RSDRch, where Rch L /
  WµeffCox(VGS-Vth)
• Effective vertical field q(Na?Ninv) / e
• NinvCox(VGS-Vth), ?1/3 for (111) and (110)
  silicon surface

Position (nm)

• Si1-xGex NWs grown over entire composition range
  (0ltxGelt1) using SiH4 and GeH4
• NW diameter varies from 10 nm to 150 nm in a
  given sample
• Measured xGe as a function of NW diameter using
  EDS in scanning TEM mode
• Ge fraction strongly dependent on NW diameter
• Empirical model based on Gibbs-Thomson effect
  provides a good fit to the data in the Ge-rich
  growth regime

Output properties of top-gated thermally-oxidized
axially-doped n-p--n SiNW FET device
Subthreshold properties of wrap-around-gate (WAG)
axially-doped n-p--n SiNW FET device
Subthreshold properties of top-gated (TG)
axially-doped n-p--n SiNW FET device
Subthreshold properties of top-gated
axially-doped n-p--n SiNW FET device

• Si/Si1-xGex axial heterostructures fabricated by
  VLS growth
• Annular dark-field scanning TEM (STEM) and EDS
  used to profile Ge composition across interfacial
  regions
• Interfacial profile measured as a function of
  nanowire diameter

Looking to the Future
Small Diameter Nanowire Device Integration

• Electrical characteristics
• Nominally-undoped 15 nm diameter SiNWs Distance
  between source and drain 600 nm
• On/Off ratio gt 102
• Subthreshold Slope 1.2 V/dec
• Four-point Resistivity 1.5104 (O-cm) _at_ Vg 0V

• Small diameter SiNWs were successfully integrated
  into the test-bed via the large-scale
  electrofluidic method by optimizing the AC field
  strength and frequency

Achievements and Plan

• Leading edge error function Trailing edge
  inverse exponential (Same as that observed in
  thin-films)

• Using our expertise in nanowire synthesis,
  processing, characterization, device fabrication
  and testing, we have demonstrated high
  performance inversion-mode semiconductor nanowire
  FETs.
• The semiconductor nanowire FETs will be used as
  diagnostic structures to study carrier mobility
  and probe the transition from bulk diffusive to
  1D confined transport as NW diameter is scaled
  down.

Source
Broader Impact

• Distinct turn-on and turn-off transients in
  Ge composition at interfaces
• Arise due to time required to change composition
  of the liquid Au-Ge-Si phase
• The leading edges (Si to Si1-xGex) are more
  abrupt than trailing edges (Si1-xGex to Si)
• Interfacial width increases with increasing
  nanowire diameter
• Due to increased time to change composition of
  larger catalyst particle

• Fundamental advances in nanowire science have the
  potential to impact the following additional
  technologies
• Homeland Security (Chemical/Biological Sensors)
• Medicine (Biological Sensors)
• Energy (Photovoltaics)

Si3N4
n Si Substrate
Gate
Drain
Financial support for this project provided by
NSF NIRT 0609282