CAD Implications of New Interconnect Technologies

1
CAD Implications of New Interconnect Technologies

• Lou Scheffer

2
Why? Interconnects dominate delay
Data from ITRS Roadmap
3
Why? Interconnects use a lot of power

• Interconnect power Total dynamic
  power

Interconnect-Power Dissipation in a
Microprocessor, N. Magen, A. Kolodny, U. Weiser,
N. Shamir, SLIP 2004
4
Lots of proposals for improving interconnect

• Improved metal-insulator systems
• 3D chip construction
• Replace copper wires by carbon nano-tubes
• Replace copper wires by optical interconnections
• Each has CAD implications

5
Traditional metal systems
6
Copper Resistivity is Getting Worse
Figures courtesy of Azad Naeemi of Georgia Tech
Scattering from rough surfaces, grain
boundaries, and impurities Copper resistivity
increases as cross-sectional dimensions scale No
known technology solution to this problem
7
Can improve the fraction due to cladding

• Cladding is needed to prevent contamination due
  to the copper
• But cladding is a high resistance material
• So process engineers are trying to make a thinner
  cladding that is still reliable

Figure courtesy of NS Nagaraj at the SRC
Interconnect Forum
8
Recent IBM announcement

• Shows the limits of improvments
• Even if we reduce K to 1, get only
• 15 power
• 30 speed

Credit IBM
9
Net results from improving conventional
interconnect

• C can be reduced slightly by lower-K and better
  etch stops and barriers
• R will get worse due to scattering at small
  widths
• Nothing we know of helps much with this
• R might get a little better due to less or better
  cladding
• Changes to CAD tools
• Must account for resistivity changing with width,
  if you do not already. This happens both from
  cladding percentage, and scattering effects
• Could have a mask that determines dielectric
  constant (as in the IBM announcement)

10
3D chips why?

• Potentially shorter interconnect

Through wafer vias
Tier 3
Tier 2
Tier 1
Picture from 3D integration research at IMEC,
Belgium.
11
CAD Implications of 3D

• Could imagine 3D placement, routing, etc.
• But this is not likely. Why?
• Enormous amounts of 2D infrastructure
• Designs partitioned already just partition into
  tiers
• Different technologies (RF, analog) on different
  tiers
• Masks will be expensive want to limit ECOs to
  single tiers
• IP will be 2D for generality
• Most likely system partitioning will divide into
  2D pieces

12
CAD implications of 3D

• If design is partitioned into tiers, existing
  layout software will work
• Area IOs technology developed for flip-chip will
  work for 3D stacking
• Need to add electrical models for cross-tier vias

Die photos from Maxim IC
13
Partitioning

• May want some fast 3D placement to suggest
  partitioning, as in 2D prototyping

14
Thermal analysis

• Harder for heat to get out
• Heat must go through routing layers (not through
  the substrate)
• May need to add (and analyze) thermal vias

15
IR drop and inductance

• Return path may be on any tier
• May require full 3D inductance calculations

This technology is fairly well developed for
Printed Circuit Boards and Multi-Chip Modules
Picture from IBM
16
Carbon nanotubes

• Why?
• May conduct better than copper
• Essentially no electromigration limits
• Better thermal conductor than copper

Courtesy of A.V. Krasheninnikov
17
Nanotubes are different electrically
3-D conductors
1-D conductors
Conventional wires Backscattering through a
series of small angle scatterings Mean free paths
30nm
Quantum Wires Very limited phase space for
scattering Mean free paths gt 1.6?m

• Resistance is a non-linear function of length
• There is an additional inductance called
  kinetic inductance

18
Electrical model - Resistance

• Quantum limited minimum R (about 7.45 kohms/tube)
• One half minimum R appears at each contact
• Electrons floating in 3D sea at the end must get
  promoted into a higher energy band to travel in
  the nano-tube, requiring energy
• Same energy dissipated when electron drops in
  energy at the end
• Transport is ballistic up to (roughly) mean free
  path, then goes up linearly
• Mean free path is proportional to diameter of tube

19
Electrical model - Resistance

• Resistance depends on length, but not linearly

Resistance
Rmin
MFP Mean Free Path
Length
20
Combining all three effects in MWNTs
Bulk copper
Figures courtesy of Azad Naeemi of Georgia Tech
For large lengths large MWNTs offer the highest
conductivity For mid-range lengths SWNT-bundles
offer the highest conductivity
21
Electrical Model Capacitance and Inductance

• Surface of nano-tube looks very different from
  copper
• But from far away, details of surface do not
  matter
• Net result Capacitance very similar to copper
  for the same shape
• Existing tools and algorithms will work well

22
Electrical Model Inductance

• Magnetic inductance is also very similar to
  copper wires
• Induced field is almost identical
• New term called kinetic inductance
• Current carried by relatively few electrons
  moving fast
• These acquire kinetic energy
• Just like the water in a pipe analogy of
  inductance you may have learned at school
• Only a self inductance, not a mutual inductance
• Dominates magnetic inductance for single
  nanotubes
• Reduces in value directly with number of tubes in
  parallel
• Not important in the bundles we will discuss, up
  to 100 GHz or so

23
Timing benefit of large diameter MWNTs depends on
length and width
Assume same aspect ratio as copper Lower
resistance and hence smaller RC delay Large speed
improvements for small wire dimensions by
SWNTs For a larger W, MWNTs with larger diameters
offer higher speeds
Relative RC Product, RCCu/RCCNT
Figures courtesy of Azad Naeemi of Georgia Tech
A. Naeemi and J. Meindl, to be presented at DAC,
June 2007
24
How nano-tubes might be used problems with
copper

• Aspect ratios as large as 1.5 to 2.5 are used to
  avoid electromigration
• This increases latency, crosstalk, power
  dissipation and dynamic delay variation
• Thickness variations caused by CMP exacerbate the
  problem

25
Thin SWNT Signal Interconnects
RC 3.5K? 1/3 metallic T1000C 0.34nm
separation Bi-layer SWNT Interconnects Worst-case
delay considered
Figures courtesy of Azad Naeemi of Georgia Tech
4x smaller lateral capacitance, 2.7x smaller
worst-case capacitance, 2x smaller average
capacitance 2x lower dynamic power dissipation
(less margin for crosstalk)
26
So when would a router use these thin layers?

• For short nets, resistance dominated by
  transistors whereas capacitance is dominated by
  interconnects and loads
• An interconnect roughly 10 gate pitch long has a
  capacitance comparable to a typical gate
• An interconnect roughly a few hundred gate
  pitches long has a resistance comparable to a
  typical gate
• Router would look at driver R, load C before
  assigning layer to nanotube or metal

27
If used for local wires, will have high R

• Dust off old technology used with polysilicon
• Short wires only
• Cannot use as a feedthrough

Weak connect Router can connect to either of
these two ends, but not both
28
Will only route one way in one layer

• Need strict router behavior
• One layer only horizontal, one only vertical
• Electromigration limits will be on vias, not
  wires
• By coincidence, matches radically restricted
  rules for lithography

Figure courtesy of Azad Naeemi of Georgia Tech
29
Optical interconnections
This is an indirect light source. Can also use a
direct source such as a semiconductor laser (but
needs other materials)
Picture courtesy of Mauro J. Kobrinsky of Intel
30
How might optical be used?

• Some routing is done with optical signals
• Waveguides can be built into silicon using
  technology similar to wires
• Overhead for transmitters and receivers, but no
  repeaters
• Makes sense only for long wires
• A lot of work underway to make transmitters and
  receivers use silicon rather than III-V compounds
• Can also be used for off-chip communication

Picture courtesy of M. Taubenblatt, IBM
31
Enormous potential bandwidth available
From the Lightwave Research Laboratory of
Columbia University
32
Lots of implications for floorplanning

• Transmitters and receivers are big
• Power optimization depends of both length and
  activity
• Latency can determine if optical is needed
• Floorplanning will need to be timing driven, even
  more so than today

33
Waveguides are big compared to wires

• 300-400 nm wide, with roughly equal spacing
• But losses (compared to wires) are low 4db/cm

High Index material
Low Index material
34
Also, can send multiple signals in one waveguide,
if wavelengths differ
Picture courtesy of Mauro J. Kobrinsky of Intel
35
Activity must be taken into account

• Electrical wires take power proportional to
  length x activity
• Optical wires depend only on activity, but have a
  large constant for the transmitter and receiver

Copper wires with different scaling rules
Picture courtesy of Mauro J. Kobrinsky of Intel
36
Signals that require low latency may need to be
optical
Picture courtesy of Mauro J. Kobrinsky of Intel
37
Transmitters/receivers are relatively big

• Will need to include in floorplanning
• Transmitters are maybe 40x5 microns
• Receiver maybe 5x5 microns today

38
Routing problem very different

• Corners may be curves, or done with mirrors
• Multiple signals in one waveguide
• Pin/layer assignment cannot simply swap a
  signal from electrical and optical, or vice-versa

39
May interact with package/board optimization

• Optical already used at these levels research
  into integrated packaging such as this from DARPA

40
New libraries and library formats

• Will need new properties for cells
• Output power. Wavelength, input sensitivity
• Likewise for layers
• Transmission vs wavelength
• Properties of splitters, mirrors, etc.
• In theory, a straightforward engineering problem
• But libraries have lots of inertia
• And sometimes political implications

41
Summary

• Four technologies in order of CAD difficulty
• Easiest is enhancements to metal-insulator
  systems
• Basically just updated coefficients R depends on
  width
• Next easiest is nano-tubes
• Modify coefficients, dust off old poly routing
  technology modify EM checks length dependent
  resistance
• Next is 3D
• New partitioning, better thermal analysis 3D
  inductance
• Hardest is optical affects almost every part
• Floorplanning, routing, layer assignment,
  libraries, etc.
• Also lots more interaction with optical package,
  board, etc.