Status of Oxford Setup

1
Status of Oxford Setup

• Matthew Chalk, Erik Devetak, Johan Fopma, Brian
  Hawes, Ben Jeffery, Nikhil Kundu, Andrei
  Nomerotski
• University of Oxford ( 18 August 2006 )

2
Oxford Test Setup

• Goals
• Fully test and exercise produced electronics,
  should improve understanding, quality and
  feedback
• Analogue readout of CPC2
• Perform additional CPC2 measurements, build up
  CCD expertise
• Experiment with power provisions for the clock
  driver with real sensor and super-capacitors

3
Oxford Test Setup
Light version of the RAL setup
4
Status

• Minimal configuration is functioning
• Sequencer based on BVM2
• Agilent LV PS
• Oxford Bias PS controlled by BVM1
• Agilent mixed-signal Oscilloscope used as ADC
• LabView code was mostly inspired by RAL examples
• Many thanks to Konstantin for help

• Main parameters
• Sequencer Master Clock 1-10MHz
• Integration time (time between triggers) 0.003 -
  0.5 sec
• Graph RG, CCD Clock and CCD analogue readout

5
Measurements X-ray signal

• Standard procedure to enhance probability to
  have a Fe55 signal need to integrate long time ?
  need to operate at low temperature
• Our setup is running so far at room temperature ?
  accumulate substantial noise from leakage current
• Reduced integration time to minimum (3 msec) and
  used accumulation feature of the scope

Background noise
Signal (approx. 15mV below the noise )
N.B. Picture taken straight from the oscilloscope
6
Measurements X-ray signal

• RMS of Raw Noise 2-4 mV
• Illuminated CPC2 with Fe55 X-ray source (5.9 keV)
• Signal 15-20 mV ? useful calibration
• 18 mV expected based on expected amplification
  etc
• 1600 e from Fe55 ? 100 e / mV
• Noise 300 e (to compare to 50-100 e at RAL
  ways to go!)
• Noise performance is poor as expected at room
  temperature and long integration time
• Had a setback using the ICS-554 PCI ADC
• Double PCI-PMC carrier does not fit in our PC ? ?
  ?
• Will exchange for a single carrier, here in a
  month
• Potentially ICS-554 will allow fast readout
  (faster than VME), it also has onboard large FPGA
  for pre-processing so further speed-up is
  possible (for ex setting a threshold and passing
  on to the PCI bus only events above the
  threshold)
• In the meantime tried to detect signal using
  scope trace readout to PC but this was too slow
• Concentrated on noise measurements

7
Noise Analysis

• Examples on noise graphs
• Different pixels have different offsets
  (pedestals)
• Software subtracts pedestals so many rows can be
  added up (right bottom graph)
• Almost no tails in noise distribution ? good fit
  by single Gaussian

8
Noise vs Integration Time

• Naively expect that leakage current is main noise
  contributor
• Ncarriers Tintegration
• Noise sqrt( Tintegration)
• Trigger rate effectively determines integration
  time
• See some dependence above 100 msec, no dependence
  below
• It looks that at smaller integration time noise
  is not caused by the leakage current ? room for
  further improvement?

9
Noise vs Master Clock Frequency

• Higher frequency effectively decreases
  integration time so this qualitatively agrees
  with previous result

10
Noise analysis

• To explain better what we measure
• Scope traces include 50 consecutive pixels (so
  50 rows of CCD)
• These 50 rows can be sampled at any location of
  CPC2
• Simultaneously 3 CCD columns are measured, see
  graph
• Amplitude for each pixel is measured at a certain
  delay wrt trigger
• Can study noise correlations between CCD rows and
  columns

11
Noise correlations

• Dnoise standard deviation of amplitude
  difference for two channels
• If no correlation expect Dnoise to increase by
  sqrt(2) wrt noise of single channel
• If absolute correlation expect Dnoise to be 0
• If absolute anti-correlation expect Dnoise to be
  doubled
• Can study
• Column Dnoise expect correlation as readings
  are taken simultaneously
• Row Dnoise expect less or no correlation as
  rows are read out at different time

12
Column Dnoise

• Took data for 12 locations 4x3 columns with
  analogue outputs times 3 row regions
• Adjacent column Dnoise Aij Ai1j
• Noise 2 mV
• Assuming no correlation between pixels ?
• 2mV/1.4100e/mV 140 e
• Uniform column Dnoise across CCD

13
Column Dnoise

• Correlation of far away columns
• Far away column Dnoise Aij AiNj
• Less correlation with far away columns

14
Row Dnoise

• Adjacent row Dnoise Aij Aij1

15
Row Dnoise

• Far away row Dnoise Aij AijN
• Limited by 50 pixel readings (scope)
• Results suggest anti-correlation
• Need further study a bit controversial
  measurement

16
Summary

• Oxford setup is up and running
• So far studied CPC2 noise at room temperature
• Setup was very useful for MB4.3 debugging
  hopefully goes to RAL in better shape than
  previous versions
• Plans
• Lower temperature
• Set up proper ADC readout
• Study signal response ? gain calibration etc
• Set up charge injection mode