Lecture 19: SIU

1
Lecture 19 SIU PIT

• Computer Engineering 211
• Spring 2002

2
MPC 555
TPU3
TPU3
Serial bus
ADC
ADC
RCPU
U-bus
U-bus System Interface Unit (USIU)
4KB SRAM
26KB SRAM
L-bus
3
MPC555 Interrupt Controller
IRQ07
SIU
RCPU
DEC
Int C O N T R O L
Level 7
I7
Level 6
TB
I6
Level 5
IRQ
I5
Level 4
I4
PIT
Level 3
I3
Level 2
I2
Level 1
I1
Level 0
I0
4
MPC555 PIT
Same as described earlier. PIT-period
(PITC1)/PIT-Clock
Different memory-mapping (then MPC 500 family)
0x2f c000
5
PIT Registers
PISCR 0x2f c240
0
13
14
15
7
8
PIRQ
PS
PIE
PITF
PTE
PIT interrupt level 1000 0000 Level 0 0100
0000 Level 1 0000 0001 Level 7
6
PIT Registers Contd.
7
Details of PowerPC 509 Interrupt Programming
PCU Peripheral control unit
L-bus interface
Address decode
Data mux
software watchdog
portQ
IRQ07
Interrupt controller
8
PCU Module Configuration Register PCUMCR
SUPV 00 S/U 01 S 10 S/U read S
write
IRQMUX 00 no multiplexing
8 IRQs 01 21 mux 16 sources
10 31 mux 24 sources
11 41 mux 32 sources
9
Interrupt Controller
RCPU
PIT
PICSR
EIE
EID
PITR
NRI
PITQIL2731
Interrupt controller
Port Q
IRQPEND
PQPAR
IRQENABLE
IRQ06
IRQAND
PQEDGDAT
PITQIL026
10
Interrupt Controller Contd.
Distinction between interrupt level and IRQ i
There are 32 levels for interrupt IRQ0, 1, 2
can be assigned any level 031 IRQ3 6 IRQ4
8 IRQ5 10 IRQ6 12 PIT assignable 031
When an interrupt occurs, its corresponding level
bit in IRQPEND is set.
0
6
IRQPEND
1
11
Interrupt Controller Registers
12
Interrupt Controller Registers
13
Interrupt Controller RegistersPITQIL
PITQUIL contains four 5-bit fields to program
interrupt level of PIT and IRQ02.
14
MPC555 Interrupt Controller
From IMB32 peripherals
L7 for 7-31
L0
L1
L2
L3
L4
L5
L6
UIPEND
External IRQ07
I1
I2
I3
I4
I5
I6
I7
I0
IRQ
Priority arbiter
8-bit vector SIVEC