Statistical Response Compaction for BIST Using Spectral Analysis

1
Statistical Response Compaction for BIST Using
Spectral Analysis

• Omar Khan and Michael L. Bushnell
• okhan_at_caip.rutgers.edu
• bushnell_at_caip.rutgers.edu
• Nanotechnology and VLSI Test Group
• CAIP Research Center
• Rutgers University
• Piscataway, New Jersey
• Funded by the National Science Foundation
• Grants CCR0098304 CCR0429774, 2001-2007

2
Purpose of this Research

• Invent a new type of response compacter for
  built-in self-testing (BIST) to
• Drastically shorten the test sequence
• Drastically reduce the test power
• Reduce the testing time and the testing cost
• Reduce the aliasing compared with the
  multiple-input signature register (MISR)
• The new compacter should use about the same
  hardware as the MISR

3
Talk Outline

• Motivation
• Prior Work
• Response Compaction using Spectral Analysis
• Simulation Results
• Conclusion

4
Motivation

• Want sequential mode BIST system
• Use Hadamard transform -- extract spectrum
• In test patterns for pattern generation
• In outputs for response compaction
• Avoid Multiple Input Signature Register (MISR)
• Aliases more from vector holding in test set
  (Nechman)
• Need spectral BIST response compactor
• Low Aliasing Probability
• Low Hardware Overhead

5
Prior Work

• Frohwerk, 1977, First use of Linear Feedback
  Shift Register (LFSR) for BIST pattern generation
• Koenemann and Mucha, 1980, Invention of Multiple
  Input Signature Register (MISR) for response
  compaction
• Gupta et al., 1980, Zero Aliasing Compression
  with generalized LFSR
• Rajski and Tyszer, 1997, Arithmetic Built-In
  Self-Test for Embedded Systems
• Pomeranz and Reddy, 2001, Improved Static Test
  Compaction for Sequential Circuits

6
Spectral BIST System
TPG Spectral Test Pattern Generator CUT
Circuit Under Test SRC Statistical (Spectral
Analysis) Response Compactor
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Spectral Analysis Using Hadamard Matrices

• Bit overlapping 2-bit Chunks
• Pre-multiplying with H(1) gives two correlation
  coefficients, one for each row
• 1st row is addition of two bits in chunk
• 2nd row is difference of two bits in chunk

and N is total elements
H(0) is 1,
0 1 1 0 1 1 1 0 0
Bit
9 8 7 6 5 4 3 2 1
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Compaction with Hadamard Matrix Spectral Analysis

• Used Hadamard matrix to analyze spectral content
  of the CUT outputs
• Any bit stream is sum of digital spectral tones
• Each a row in Hadamard matrix
• Used H(1) (2X2 matrix) for compaction
• Calculated auto-correlation and cross-correlation
  with 2 tones (rows) of H(1)
• Statistical Response Compacters (SRCs) store
  correlation coefficients as signature
• Spectrum in terms of tones of H(1)

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Advantages of Spectral BIST System

• System uses Zhang et al.s spectral test pattern
  generator in sequential mode
• Test pattern length is considerably shorter
• Shorter test length will save test time and power
• Zero aliasing in SRC1
• Hardware overhead in SRC2 lower than MISR in some
  circuits and comparable in other circuits

10
Example

• Spectral content of PO1 extracted by 1st row is 4
  as demonstrated by the example below

Bit stream at POs of a CUT
2 X 2 Hadamard Matrix
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PO1 Spectral Content From Rows 1 2
Spectra for Four POs
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Statistical Response Compactor 1 (SRC1)

• Consists of 4-bit tone counter and end around
  carry
• One needed for each Primary Output (PO)
• Signal sub is asserted when the 2nd tone is
  being calculated
• 2 passes one for each tone
• Records auto-correlation of bits at a PO

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Architecture of SRC1
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Statistical Response Compactor 2 (SRC2)

• In 2nd implementation used cross-correlation
  among adjacent PO pairs
• Accumulate spectra in two counters for entire
  circuit
• Add Counter
• Subtract Counter
• Eliminates flip-flops for prior PO values

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Architecture of SRC2
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Statistical Response Compactor 5 (SRC5)

• Auto-correlate each PO and then cross-correlate
  pairs of POs (figure on next slide)
• Auto-correlation is done using Hadamard transform
  block (HT Block)

Cin
(sub)
D
Q
A
Sum
FA
CLK
B
Cout
POn
sub
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Architecture of SRC5
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SRC1 Results
No. of Faults Lost
No Aliasing by SRC1 on any Benchmark Circuit
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SRC2 Results
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SRC3 Results
Implements only 1st tone of SRC1
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SRC4 Results
No. of Faults Lost
Implements only 2nd tone of SRC1
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SRC5 Results
No. of Faults Lost
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Hardware Overhead Length

• Average response compacter hardware overhead
• Overhead for SRC2 is much lower than MISR
• Much shorter test length for spectral TPG

24
SRC Conclusions

• Test length is 10.9 of LFSR test length (no
  reseeding)
• Saves test time and power
• Zero aliasing in SRC1 on ISCAS 89 circuits
• Each tone (SRC3 and SRC4) aliases, but never for
  same faults
• SRC2 is best -- 59 of MISR overhead
• Reason MISR has 1 FF per PO but SRC2 needs only
  4 FFs in entire compacter
• Relatively low aliasing
• SRC5 aliases more than SRC2 -- uses more hardware