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Spartan3 Framework supporting Digital Design, DSP

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... are displayed in 8-bit colour or greyscale depending on ... Quadrant 2. Quadrant 1. Quadrant 0 (64k x 32-bit. locations) SRAM Memory Map. max 64k x 32-bits ... – PowerPoint PPT presentation

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Title: Spartan3 Framework supporting Digital Design, DSP


1
Spartan-3 Framework supporting Digital Design,
DSP Image Processing Projects and Courses
Dr Fearghal Morgan, NUI Galway
  • Customisable user module (DSPBlk)
  • Host GUI with USB and Serial interface options
  • Demos Delta frame generation, Colour inversion,
    flip image, warp image, morph image, colour
    change, edge detection (in progress)

Spartan-3 FPGA
Host GUI
USB daughtercard
2
appliedVHDL Design Structure
  • The FPGA system contains the following blocks
  • host I/F (usb and serial options)
  • CSR block
  • SRAM controller
  • display ctrlr
  • dspBlk
  • user-defined
  • currently including a range of basic image
    processing tasks, supporting up to 512x512 pixel
    images, grayscale and colour

3
System CSRs
  •       CSR 0 Top 2 bits of current SRAM Address
    (1716), SRAM quadrant select
  •       1 SRAM Start address byte (158)
  •       2 SRAM Start address byte (70)
  •       3 SRAM End address byte (158)
  •       4 SRAM End address byte (70)
  •       5 Number of SRAM 32-bit longwords to be
    processed byte (158)
  •       6 Number of SRAM 32-bit longwords to be
    processed byte (70)
  •       7 DSP function
  •       8 Colour change DSP value
  •       9 Max pixel value check for both images
    during DSP

4
Configure Spartan 3
  • Refernce demo configuration files are located in
    directory demoBitSVFFiles
  • The USB port version is fast and vitalwhen
    processing images larger than 64x64
  • The Serial port version is slow but functions
    well for small image sizes
  • The USB interface requires connection of USB
    daughter card to Spartan-3 board
  • Serial port implementation
  • Configure using
  • appliedVHDLUART.svf if using adept confguration
    interface
  • appliedVHDLUART.bit if using parallel IV cable
  • USB port implementation
  • Configure using
  • appliedVHDLUSBSimple.svf if using adept
    confguration interface
  • appliedVHDLUSBSimple.bit if using parallel IV
    cable
  • Source VHDL code is the same in both
    appliedVHDLUSBSimple and appliedVHDLUART except
  • for the host interface blkck
  • All VHDL code is contained in folder VHDL.

5
Execute Host GUI
  • Unzip file VB.zip  
  • Execute appliedVhdlBoth.exe in the VB folder (the
    .exe calls other programs in the VB directory).
  • The GUI system will operate fully if the Spartan
    3 is connected using either the serial or USB
    port. A warning message is issued if the serial
    port connection is not correctly connected.
  • If using serial port, ensure that connection is
    correct
  • If using USB port, ignore warning message and
    select USB option on GUI
  • On startup of the GUI, a CSR r/w test is
    performed in the background to verify the above.
    Note that CSR(0) is automatically cleared to 0 on
    GUI startup.
  • If performing image processing, several image
    files (.bmp) are available in the VB directory.
    These must be located in the directory containing
    appliedVHDLBoth.exe.
  • The USB implementation is very fast. While using
    the serial port implementation, testing on the
    smaller image (8, or 64 .bmps) is
    recommended.
  • Select colour to open an image in colour mode

6
SRAM r/w controls
CSR r/w controls
Select serial connection or USB
7
SRAM r/w
  • 256k x 32-bit onboard SRAM locations.
  • SRAM is divided into 4 quadrants of size
    256kBytes
  • Quadrant selected using the 2 top bits of SRAM
    address (defined in CSR 0 prior to an SRAM access
  • Individual SRAM rd/write access control
  • The SRAM address field must include 5 digits
    (corresponding to an 18-bit SRAM address value)
  • GUI sets CSR 1-4 accordingly
  • The SRAM write data field must include 8 digits
    (32-bits)
  • Block SRAM reads and writes (to/from file) see
    next slide
  • Filename, and number of 32-bit accesses is
    defined in GUI and start address
  • GUI sets CSR 1-4 accordingly
  • eg reading from address 0FFFF.  
  • Quadrant is set to 0, Start address FFFF, end
    address is FFFF
  • 4 bytes are then read from this location, SENT TO
    HOST and displayed in the relevant field in the
    GUI
  • For writes to SRAM from a file, a .raw data file
    must first exist
  • A .raw file example is included in VB directory
    for reference
  • All files are stored as raw format as only bytes
    are saved and read.
  • The execute button starts the process and will
    inform of any problems.

8
Write from file to SRAM
  • File test.raw is provided in directory VB holding
    data FFFFFFFF.
  • This can be modified or extended as source data
    for performing a data write to SRAM

9
Image processing function
  • CLICK ON Open image 1 read first image
    (browse)   - it is automatically displayed
  • Image 1 is converted to raw format and
    transferred from host to SRAM quadrant 0 (max
    256KBytes)
  • CLICK ON Open image 2 read second image
    (browse)  - it is automatically displayed
  • Image 2 is converted to raw format and
    transferred from host to SRAM quadrant 1 (max
    256KBytes)
  • Note that two images must always be read even
    though some image processing functions only
    operate on image 1
  • Images are displayed in 8-bit colour or greyscale
    depending on the chosen option in Colour Choice.
  • The type of image processing depends on the
    option chosen in the DSPfunctions menu.
  • Image Processing can then be activated
  • Results (stored in SRAM quadrant 2) are
    automatically transferred to host and displayed.
  • In the top right corner of the GUI the DSP
    options are available. Any can be chosen prior to
    pressing the Execute image processing button
  • The GUI extracts the number of SRAM 32-bit
    longwords comprising the image(s) to be processed
    and programs CSR 5-6 accordingly. Selected DSP
    function is written to CSR 7.
  • The DSP function operates on the defined number
    of 32-bit SRAM longwords in the image starting
    from quadrant address 0

10
Demo using EENUIGImage1_512x512.bmp EENUIGImage2_
512x512.bmp (slightly shifted version of the
above image) Image processing, colour mode,,
serial port (very slow !), delta frame generation
11
Demo using EENUIGImage1_512x512.bmp EENUIGImage2_
512x512.bmp (slightly shifted version of the
above image) Image processing, colour mode,,
serial port (very slow !), invert colours
12
Demo using EENUIGImage1_512x512.bmp EENUIGImage2_
512x512.bmp (slightly shifted version of the
above image) Image processing, colour mode,,
serial port (very slow !), flip image
13
Miscellaneous points
  • USB daughter card rewiring issue
  • Note that the USB daughtercard has been rewired
    see the .ucf file in the VHDL directory for
    pinout and picture of daughter card/Spartan 3
    card on the first slide. This may be different
    for the latest revision of the USB daughtercard
    or other wirting/.ucf workarounds.
  • Images must contain an even number of pixels (2
    0), i.e., always a whole number of 32-bit words
    to be transferred. 
  • BMP images up to size 512x512 are supported (256k
    bytes or 1/4 the size of the SRAM on the
    Spartan-3 board)
  • 24-bit colour images format must be used. This is
    translated to 8-bit image (indexed with colours
    chosen at fixed intervals to give as many
    different colours as possible, sorted by hue to
    give a natural progression of colours

14
Demo using image1e_8x8pixel.bmp and
image2e_8x8pixel.bmp Grayscale mode, delta frame
generation
15
Demo using stripes1_64x64.bmp and
stripes2_64x64.bmp Grayscale mode, delta frame
generation
16
Demo using tea.bmp (for both images) Image
processing, colour mode, USB port (fast !),
invert colours
17
Demo using colour8x8Image1 and colour8x8Image2
.bmp Image processing, colour mode, serial
port, delta fram generation
18
Alternative DSP Functions
  • A wide variety of DSP functions can be included,
    supported by CSR
  • and SRAM resources, e.g.,
  • Audio processing
  • Image processing
  • Encryption, coding algorithms
  • Games
  • The DSPBlk and GUI enables straightforward
    implementation of such projects

19
SRAM structure and DSP Delta Image Task Execution
Image 1 in SRAM quadrant 0, image 2 in SRAM
quadrant 1Quadrant size 64k 32-bit words
Perform delta frame generation, i.e., (image 2
image 1)Write result to SRAM quadrant 3 (same
size as original images)
SRAM Memory Map
11 1111 1111 1111 1111 (3FFFFh) 11 0000 0000
0000 0000 (30000h) 10 1111 1111 1111 1111
(2FFFFh) 10 0000 0000 0000 0000 (20000h)01
1111 1111 1111 1111 (1FFFFh) 01 0000
0000 0000 0000 (10000h) 00 1111 1111 1111 1111
(0FFFFh) 00 0000 0000 0000 0000 (00000h)
Quadrant 3 Quadrant 2 Quadrant
1 Quadrant 0(64k x 32-bitlocations)
max 64k x 32-bits
0044440 (delta result)
FF8888FF (image 2 data longword)
FF4444FF (image 1 data longword)
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