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CSC 345 Computer Architecture
Jane Huang Lecture 10 Microprogrammed
ControlReview
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The primitive components of an instruction

1. A program consists of a sequence of instruction
   cycles.
2. Each instruction cycle is made up of a number of
   smaller units.(fetch, indirect, execute,
   interrupt etc).
3. A further decomposition into micro-operations is
   possible.

Micro-ops are the atomic operations of the
processor.
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t1 MAR ? (PC) t2 MBR ? Memory PC ?
PC 1 t3 IR ? (MBR)

• Control Signals
• Three types of control signals
• To activate an ALU function
• To activate a data path
• External signals on system bus or other external
  interface.
• Signals are applied as binary inputs to
  individual logic gates.
• Fetch Cycle
• 1st step is to transfer contents of PC to
  MAR.Control unit activates the control signals
  that open the gates between the bits of the PC
  and the bits of the MAR.
• 2nd step is to read a word from memory into the
  MBR and increment the PC.
• Control signal to open gates allowing contents of
  MAR onto the address bus.
• Memory read control signal on the control bus.
• Control signal that opens gates allowing the
  contents of the data bus to be stored in the MBR
• Control signals to logic that add 1 to PC and
  store results back to PC.

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Control Signals Control unit needs

• Inputs to sense the state of the system

• Outputs to control the behavior of the system

• Internal logic to perform sequencing and
  execution.

Control Unit
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• Hardwired implementation
• Control unit takes the opcode from the
  instruction register.
• A decoder is used to generate a unique signal for
  each opcode.
• Each of the 2n different input patterns will
  activate a unique output.

Instruction Register
Decoder
Control Unit
Timinggenerator
Clock
Flags
Control Signals
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• Microprogrammed Control
• Common in CISC processors
• Each microinstruction is executed by activating a
  specific set of control signals.
• Each control signal could be represented by a
  single bit in a control word. (1activate
  signal, 0no signal).
• A sequence of control words could be strung
  together to represent the sequence of
  micro-operations performed by the control unit.
• This sequence is NOT fixed therefore we need a
  control memory containing uniquely addressable
  control words.
• Each control word also contains the address of
  the next control word plus a condition.
• ? Horizontal microinstruction.

Internal CPU control signals
System BusControl Sigs.
JumpCond
Microinstructionaddress
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• Implementing a Horizontal Instruction
• One bit in the CPU control signal field to
  represent each control line.
• One bit in the System bus field to represent each
  System Bus control line.
• Condition field (unconditional, zero, overflow,
  indirect bit)
• Next microinstruction address field.
• Executing a Microinstruction
• Turn on all necessary control lines by setting
  the bit to 1.
• If the condition is false, execute the next
  microinstruction in sequence.
• If the condition is true, execute the
  microinstruction at the address pointed to by the
  microinstruction address.

Internal CPU control signals
System BusControl Sigs.
JumpCond
Microinstructionaddress
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? ?Jump to indirect or execute
Fetch cycle routine
? ?Jump to execute
Indirect cycle routine
? ?Jump to fetch
Interrupt cycle routine
Jump to opcode routine
Execute cycle beginning
? ?Jump to fetch or interrupt
AND routine
? ?Jump to fetch or interrupt
ADD routine
? ?
? ?

• Control words are arranged within a control
  memory.
• Microinstructions within a routine are executed
  sequentially.
• Each routine ends with a branch or jump
  instruction.

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• Sequencing logic selects the next address and
  places it into the control address register.
• The address is used to select a word from control
  memory.
• A read signal is issued.
• The control word is placed into the control
  buffer register.
• Reading a word is synonymous with executing the
  microinstruction.

Connection to control lines.
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• What are the roles of the two
• decoders?
• Upper decoder translates the opcode of the IR
  into a control memory address.
• Lower decoder supports a different type of
  microinstruction called a vertical
  microinstruction.
• In a vertical instruction a code is used for
  each action and must be decoded into control
  signals.

Decoder
Decoder
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Decoders

• A combinatorial circuit with a number of output
  lines.
• Only one output line is asserted at any time.
• The asserted output line is selected by the
  inputs.
• A decoder has n inputs and 2n outputs.

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Wilkes Control
From IR
Clock
Register 2
Clock
Register 1
Addressdecoder
Clock
ConditionalSignal
Control Signals
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• Microinstruction Sequencing
• Two major design issues
• Minimizing the size of the control memory to
  reduce cost.
• Execute microinstructions as fast as possible.
• Next instruction obtained from
• Instruction register (occurs only once per
  instruction cycle)
• Next sequential address(most common within a
  sequence of microinstructions)
• Branch(end of sequence and for conditional
  instructions).

• Sequencing Techniques
• Major issue is HOW the next control memory
  address will be generated
• Three general categories of solutions
• Two address fields
• Single address field
• Variable format.

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• Two Address Fields
• Control signals sent to a multiplexer to select
  one of the two addresses. Single address field
• Simpler
• - Requires more bits in microinstruction

Control Signals
Address 1
Address 2
Multiplexer
BranchLogic
AddressSelection
To CAR
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Multiplexer Implementation
S2 S1 F
0 0 D0
0 1 D1
1 0 D2
1 1 D3

• Used in digital circuits to control signal and
  data routing.
• Loading of the PC in which the value may come
  from
• Binary counter
• IR
• Output of ALU

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• Single Address Field
• With a single address field the next address is
  obtained from address field, IR code, or next
  sequential address.
• Option determined by the address-selection
  signals.
• - Address field is often NOT used.

• Variable format
• Two different formats.
• One bit specifies the format being used.
• One format all remaining bits are control
  signals.
• Second format used for branches.
• - One entire cycle consumed with each branch
  microinstruction.Whereas other approaches
  integrate address generation and control signal
  generation within the same cycle.

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• Address Generation
• How is the next address generated?
• Two-field ? Mapping
• Unconditional branch ? addition
• Conditional branch ? Residual control
• Depends on
• ALU flags
• Part of the opcode or address mode fields
• Parts of the selected register (such as the sign
  bit)
• Status bits within the control unit.

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• Final Exam Topics
• Hamming code problems
• Cache / Memory organization
• Booths Algorithm for multiplication
• Instruction formats and design (Chapter 11)
• Instruction Pipelining (Chapter 12)
• Instruction Level Parallelism
• RISC
• Microcontrol including hardwired and
  microprogramming.
• Multiplexers Decoders
• (Remainder of tonights class will be designated
  to review).