Hardware/Software System Design and Validation

1
Hardware/Software System Design and
Validation Dr. Xiaoyu Song http//web.cecs.pdx.ed
u/song/

• Networked Sensors Architecture Platform based on
  Component-based Co-Verification
• A practical networked sensor architecture runs
  in the hardware software co-verification engine.
  Microsoft Research Giano and Mentor Graphics
  Seamless CVE are the two target verification
  environments. The architecture is platform
  dependent which can be applied to different
  applications such as home intelligence sensor,
  Bio-medical sensors, environmental sensors, and
  automobile sensors. The design is constructed
  with the component-based approach. The approach
  enforces both hardware IPs and software
  components reusability while maintaining a clear
  abstraction view for the system developers.
  Matlab and Simulink are used to construct a real
  world simulation environment for both sensor and
  network components. Low power consumption is
  considered as the system requirements is
  developed. The goal of this project is to enhance
  the co-verification environment as practical and
  realistic as possible.

F. He, X. Song, et al. Probabilistic optimization
for FPGA board level routing problems. IEEE
Transactions on Circuits and Systems II, 53(4),
264-268, 2006. W. Hung, X. Song, G. Yang, et al.
Optimal synthesis of multiple output Boolean
functions using a set of quantum gates by
symbolic reachability analysis. IEEE Transactions
on Computer-Aided Design, 25(9), 1652-1663,
2006.. W. Hung, X. Song. Routability checking for
three-dimensional architectures. IEEE
Transactions on Very Large Scale Integration
Systems, 12(12), 1371-1374, 2004. L. Cheng, W.
Hung, G. Yang, X. Song. Congestion estimation for
3D circuit architectures. IEEE Transactions on
Circuits and Systems II, 51(12), 655-659,
2004. W. Hung, X. Song. Segmented channel routing
via satisfiability. ACM Transactions on Design
Automation of Electronic Systems (TODAES), 9(4),
517-528, 2004. X. Song, et al. Board-level
multiterminal net assignment for the partial
cross-bar architecture. IEEE Transactions on VLSI
Systems, 11(3), 511-514, 2003. W. Hung, X. Song,
E. Aboulhamid. BDD variable ordering by scatter
search. IEEE Transactions on Computer-Aided
Design, 21(8), 974-979, 2002. Y. Wang, C. Pai,
X. Song. The design of hybrid carry-lookahead/carr
y-select adders. IEEE Transactions on Circuits
and Systems-II, 49(1), 16-24, 2001. Y. Wang, X.
Song, M. Aboulhamid. Adder based residue to
binary number converters. IEEE Transactions on
Signal Processing, 50(7), July, 2002. X. Song,
Y. Tang, D. Zhou, Y. Wang. Wire space estimation
and routability analysis for gate array chips.
IEEE Transactions on Computer-Aided Design,
19(5), May 2000. X. Song and Y. Wang. On the
crossing distribution problem. ACM Transactions
on Design Automation of Electronic Systems
(TODAES), 4(1), 39-51, 1999. S. Tahar, X. Song,
E. Cerny, Z. Zhou, M. Langevin. Formal
verification of an ATM switch fabric using
multiway decision graphs. IEEE Transactions on
Computer-Aided Design, 18(7), 956-972, July 1999.
Y. Tang, X. Song, Y. Wang. Diagnosis of
clustered faults for identical degree topologies.
IEEE Transactions on Computer-Aided Design,
18(8), August 1999. Y. Tang and X. Song.
Diagnosis for arbitrarily connected parallel
computers. IEEE Transactions on Computers, 48(7),
July 1999.

• Formal Verification by Generalized Symbolic
  Trajectory Evaluation, Intel
• Generalized symbolic trajectory evaluation
  (GSTE) is an extension of symbolic trajectory
  evaluation (STE). STE can handle large,
  industrial design and has been actively used in
  Intel, HP, IBM, and Motorola. GSTE was originally
  developed at Intel and has successfully
  demonstrated its powerful capacity in formal
  verification of digital systems. The goal of the
  project is to enhance the GSTE verification
  capability for complex system designs.

• Scalable Co-Verification Based on Hardware IPs
  and Software Component, SRC
• The objective of the project is to develop a
  component-based approach to scalable hardware and
  software co-verification of embedded systems
  using formal methods such as model checking. The
  method unifies the concepts of hardware IPs and
  software components, leverages advances in
  assertion-based verification, extends
  effectiveness of compositional model checking for
  system-level co-verification, and facilitates
  verification reuse.