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Evolution of Synthetic RTL Benchmark Circuits
with Predefined Testability
Tomas Pecenka, Lukas Sekanina, Zdenek Kotasek
Brno University of Technology, Faculty of
Information Technology Božetechova 2, 612 66
Brno kotasek_at_fit.vutbr.cz July 14, 2008
Humies 2008, Atlanta
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Our entry

• a set of benchmark digital circuits designed
  using an EA
• These benchmark circuits
• are intended for validation of CAD tools used in
  the area of digital circuits testing,
• have a predefined structure and level of
  testability,
• are the most complex benchmark circuits with an
  optional level of testability.
• Publication
• Pecenka, T., Sekanina, L., Kotasek, Z. Evolution
  of Synthetic RTL Benchmark Circuits with
  Predefined Testability. ACM Transactions on
  Design Automation of Electronic Systems (TODAES).
  Vol 13, No 3, 2008, 21 pages

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Overview
CAD tools for optimization of area, timing,
power consumption,
A circuit under design
CAD tool for testability analysis
Is the tool correct? The tool is validated using
a set of benchmark circuits. The benchmarks
should reveal weak points of used testability
analysis (TA) algorithms.
Circuit modification in order to improve the
testability
level of testability
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Existing Benchmark Circuits

• Real-world circuits
• ISCAS85, ISCAS89, ITC99, ITC02
• max. 231,320 gates and 6,642 FFs
• Synthetic sets
• mainly composed of above-mentioned circuits
• see references in TODAES paper
• Main problem
• The benchmark sets used till now do not provide
  circuits with various levels of
  testability/complexity, which is important for
  consistent validation of testability analysis
  methods.
• Our benchmarks the starting testability
  parameters are known gt it can be derived how the
  particular methodology improved testability and
  what is the size of the additional hardware.

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Proposed benchmark circuits

• EA is used to design benchmark circuits according
  to user specification
• Input type of components, the number of I/O,
  testability requirements, etc.
• Output RTL circuit with required complexity and
  testability
• Benchmark set
• 24 circuits from 2k gates to 1,2 M gates (after
  synthesis), four levels of testability 0, 33,
  66, 100
• 11 circuits 108k gates, 11 levels of testability
• In our methodology, evolutionary circuit design
  at the functional level is used (thousands of
  components in a circuit)
• In the fitness function, the testability is
  calculated (quadratic time complexity).
• Testability of evolved circuits is validated
  using a commercial CAD tool.

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What we claim

• D The proposed method was accepted as a new
  solution for design of synthetic benchmark
  circuits by one of prominent journals (ACM
  TODAES) in the field of design and test of
  digital circuits. Proposed set of benchmarks was
  accepted independently of the fact that it was
  mechanically created.
• G Engineers have proposed various benchmark
  circuits in the area of digital circuits testing
  for many years. The main problem in their design
  is the need for simultaneous high complexity and
  controlled testability. Hence, the problem is
  seen as of indisputable difficulty in its field.
  The proposed method is able to provide the most
  complex circuits with a known level of
  testability.

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Why we should win Humies 2008 (1)

• A new concept was proposed for validation of
  testability analysis methods.
• Instead of the use of somehow created benchmark
  sets, we can generate a well-targeted set of
  benchmark circuits which can systematically
  validate crucial features of TA methods.
• optional complexity of benchmark circuits
• optional testability of benchmark circuits
• Important We did not improve an existing
  solution only, we proposed a completely new
  concept.

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Why we should win Humies 2008 (2)

• The result was accepted as an innovation outside
  the EA community, independently of the fact that
  it was created by EA.
• In the field of digital circuits testing, an
  extremely high competition can be observed (more
  than 50 years of development).
• Many well-performing approaches have been
  proposed for this particular problem.
• The community is really conservative and
  pragmatic with respect to completely new
  approaches and methodologies.
• Have you attended a hardware-oriented conference?
  Many people do wear a tie there. Why?
• Important We have not presented our solution
  only to the EA community!
• Pecenka, T., Sekanina, L., Kotasek, Z. Evolution
  of Synthetic RTL Benchmark Circuits with
  Predefined Testability. ACM Transactions on
  Design Automation of Electronic Systems. Vol 13,
  No 3, 2008, 21 pages

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Why we should win Humies 2008 (3)

• The result strongly benefits from the use of the
  evolutionary approach.
• As benchmark circuits are designed by means of
  the EA, they can contain constructions which do
  not usually appear in the circuits designed by
  classical design techniques.
• Thus, the use of evolved benchmark circuits in
  the process of evaluating new TA tools can reveal
  problems that remain hidden when conventional
  benchmark circuits are used.
• A story with one of commercial ATPG tools
• Important We have really exploited the power of
  evolutionary design!

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Why we should win Humies 2008 (4)

• We evolved the largest objects (i.e. circuits
  containing more than 1.2M gates after synthesis)
  that have probably been created by an EA ever.
• A promising application area was identified for
  evolvable hardware Instead of function,
  structural properties of circuits can be sought
  by an EA!
• Important We have an interesting contribution
  into the evolvable hardware field.

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Why we should win Humies 2008 (5)

• In what ways does this paper advance the field?
• the issue of making available benchmark
  circuits with the complexity compatible to
  state-of-the-art digital designs is relevant
• To my knowledge, an original contribution to the
  area of the automated design of benchmark
  circuits for evaluation of Design-For-Testability
  methods.
• Anonymous reviewer

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Thank you for your attention!