Cache performance evaluation benchmarks

1
Cache performance evaluation benchmarks

• Santanu Chatterjee and Gong Zhang
• Dept of computer science and Engg.
• University of Notre Dame

2
Cache

• An important technique to reduce bus traffic and
  increase system throughput
• Spatial locality
• Temporal locality
• Integrated part of almost all high performance
  microprocessors
• improves access performance
• reduce latency
• one pervasive design technology for all levels of
  system design

3
cache performance and applications

• Multimedia
• reduce the raw required memory bandwidth to 3
  15 times
• Network processor
• temporal locality in the network packet streams.
• improving packet forwarding performance
• Database
• great gap between RAM and disk access time.
• database caching
• disk caching

4
Goals

• Developing a set of synthetic, high-level
  benchmarks to evaluate cache performance.
• Benchmark codes will be used to measure cache
  latency and bandwidth on Intel Pentium 4 and Sun
  Ultra-SparcIII architecture.
• Intel Pentium 4 platform based on
  Hyper-Threading(HT) technology.
• -on-die L1 data cache along with 12KB
  instruction cache.
• -Multi-threaded model results in
  increased cache access.

5
Goals

• Sun Ultra-SparcIII based on 100KB on-die L1
  cache, 1-way 4-8 MB off-die L2 cache.
• Incorporates write cache to reduce store traffic
  to L2 cache.
• Benchmark codes will be used to evaluate both
  uni-processor and symmetric multi-processor (SMP)
  platforms to compare the results.