EEE515J1 ASICs and DIGITAL DESIGN

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EEE515J1ASICs and DIGITAL DESIGN Designing FSMs
Ian McCrum Room 5D03B Tel [phone] voice mail
on 6th ring Email IJ.McCrum_at_Ulster.ac.uk Web
site http//www.eej.ulst.ac.uk
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Example 2A A FSM with Inputs Polaris
Missile Launcher (D-types, straight binary,
Output decoder)
Assume 2 officers must supply an input to a
system to launch the missile, any false code
causes an abort.
There is a flaw/bug/feature in this design. A
common problem in FSMs is to specify EXACTLY when
the output is to occur, in time
A sequence of 11,11,11 ltBANGgt (Missile launches
at the instant of ENTERING red alert, should be
on exit!)
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PRES STATE (state bits ZY) PRES STATE (state bits ZY) PRES STATE (state bits ZY) I/ps AB Next ST DETAIL FOR BIT Z DETAIL FOR BIT Z DETAIL FOR BIT Y DETAIL FOR BIT Y OUTPUT
1 P 00 00 P 00 RESET 0 RESET 0 0
2 P 00 01 P 00 RESET 0 RESET 0 0
3 P 00 10 P 00 RESET 0 RESET 0 0
4 P 00 11 Q 01 RESET 0 SET 1 0
5 Q 01 00 P 00 RESET 0 RESET 0 0
6 Q 01 01 P 00 RESET 0 RESET 0 0
7 Q 01 10 P 00 RESET 0 RESET 0 0
8 Q 01 11 R 10 SET 1 RESET 0 0
9 R 10 00 P 00 RESET 0 RESET 0 0
10 R 10 01 P 00 RESET 0 RESET 0 0
11 R 10 10 P 00 RESET 0 RESET 0 0
12 R 10 11 S 11 SET 1 SET 1 0
13 S 11 00 P 00 RESET 0 RESET 0 0
14 S 11 01 P 00 RESET 0 RESET 0 0
15 S 11 10 P 00 RESET 0 RESET 0 0
16 S 11 11 S 11 SET 1 SET 1 1
The equations to make this machine will require
detecting 4 different on-terms /Z/YAB /ZYAB Z/YAB
ZYAB We also need two three input or gates Cost
66334444 34p
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Pulse Generators The generic family

• consider carefully the detailed timing of i/p and
  o/p,
• Is the input to trigger when the input is high,
  or when a low to high transition occurs on the
  input level triggered or edge triggered. What
  polarity is required (though I will only cover
  low-high or high triggers here)
• Exactly when is the output to go high? Normally
  at the first active clock transition after the
  input trigger condition is met.
• an example follows of a circuit which responds to
  a low to high transition and generates one pulse.
  The input is allowed to stay high but only one
  pulse is ever generated. Only when the input goes
  low is it again armed, thus it is truly edge
  triggered and is not re-triggerable. We assume
  the input can only change infrequently and that
  the clock is much faster than the period of input
  changes.

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• The development of the state diagrams evolves
  from the sequences above. Ensure you can follow
  what each does.
• The last diagram is best, though even this
  assumes the input does not go low and then high
  again before the pulse completes its output
• A detailed timing diagram is better at
  representing exactly what is desired.
• TUT QUESTIONL5(a) develop circuits to o/p 3
  pulses
• TUT QUESTIONL5(b) develop circuits to o/p 5
  pulses

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Quick ways of designing machines The one-Hot
method

• to design any finite state machine (FSM) using
  the one-hot method you use one D-type flip-flop
  per state, you must use D-types for the method to
  work.
• You must also use the special state code
• 000..0001, 000..0010, 000..0100 etc, I.e n-1
  zeroes and a single 1, (called the HOT
  state!)
• Variations do exist, ONE-HOTZ and TWO-HOT for
  instance, but we will only deal with one-hot
  here.
• The secret to the method is to look carefully at
  the state diagram, for each state you will write
  down a term for every arrowhead entering that
  state.

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e.g Pulse Generator using one-hot
0
A/0
B/1
1
X
0
C/0
1

• A.d A /I C /I Cost 6222 12
• B.d A I Cost 62 8
• C.d C I B Cost 62210
• O/p B

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Summary Week 4
You can design counters that count up (no inputs)
You can design counters that can hold or count
You can design counters that can count up/down
or reset
You can design counters with D-type flipflops
You can design counters with JK-type flipflops
You can design using a state assignment related
to the desired outputs
You can design pulse generators
You can design using a straight binary state
assignment
You can design using a one-hot state assignment
You can cascade counters synchronously
You can appreciate why synchronous counters are
better than asynchronous counters
You can use Quartus to design multiple sheet
designs that use BUSes and develop your own
library parts
Next comes VHDL