XTRP Hardware

1
XTRP Hardware

• Mike Kasten
• University of Illinois
• 2/24/00

2
2 XFT linkers
CDF clock
L1 calorimetry
L1 muon
L2 trigger
SVT
Data board transition module (x12)
Clock/control transition module
Level1 Request
Clock/control board
Track Data
Data board (x12)
30 (2 wedges)
Data boards (duplicates)
132 ns 33ns clocks
12 data boards
XTRP I/O
The core XTRP System
Internal communication
3
XTRP Teststand 1 Pre-crate

• Custom Backplane
• Initial power-up
• Boot PROM
• VME emulation
• Signals via Unidig Module
• C code
• Power measurement

U of Illinois
4
XTRP Teststand 1 VME crate

• Successfully completed VME transactions
• Write/Read registers
• Load extrapolation RAMs
• Benchtop accessibility VME emulation were
  extremely helpful for initial debugging
• This teststand will provide initial testing
  infrastructure for new VME boards

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XTRP Teststand 2 VME crate

• VIPA-style Test Crate at U of Illinois
• VME access
• Write/Read registers
• Load extrapolation RAMs
• Multi-board system
• Controller / TestClock / Clock Control / Data
• Send clock signals from Clock Board to Data Board
• Step data through Data Board (slow clock)
• Software Development
• DataBSim.java (Data Board simulator)
• XtrpExpertPanel.java (Test engine)

6
XTRP Functional Clock Test
TestClock
CLOCK TEST
132ns, 33ns, Sync Signals
132ns Clock
Data Board
Clock Board
VME write (Test Clock)
132ns, 33ns, Sync Signals
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Functional Data Test Procedure

• Set up Data Board Clock Board
• Repeat N times
• Load XFT Simulation data into Data Board
• Increment Data Board clock via Clock Board
• Increment Simulator
• Compare Data Board versus Simulator
• Debug

8
XTRP Functional Data Test
VME write XFT Simulation Data
VME write Test Clock
Data Board
Clock Board
STEPPED 132ns, 33ns, Sync Signals
VME read compare to Simulation
9
XTRP Teststand 2 VME crate

• Data Board II is necessary
• simple reroutes 100
• power supply pins (64 identical ICs )
• various
• Mechanical compliance
• Improvements (JTAG buffering)
• Data Board I lives on
• Completely Functional
• Acceptable to use for B0 integration tests
• Clock Control Board is OK (so far)
• Corrections do exist 25 total wires
• Relayout not planned

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XTRP Teststand 3 Wilson Hall

• Multi-crate system
• XFT CDF-style Crate
• Test Clock / Clock Splitter / Controller / TRACER
• LinkerTester
• Linker / Output Modules
• XTRP VIPA-style Crate
• Controller / TRACER
• Data Board
• Clock Control Board
• Much much more Software Development

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XTRP Tests
DATA TEST
gt1,000,000 clocks error free
Linker(2) Output Formatters
VME write
VME read compare to Simulation
Data transferred at full speed for 250 clocks
VME read from Pipe FPGAs
Linkertester Input Fifos
Data Board
CAL/MUON Data
INPUT TEST
gt100,000,000 clocks errors x000000 to xFFFFFF
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XTRP Tests
VME write
Output Fifos
Linkers (2)
Linkertesters (2)
Data transferred at full speed for 10k clocks
VME read compare to Simulation
Data Board
Input Fifos
gt10,000,000 clocks error free
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XTRP Tests
VME write
Output Fifos
Linkertester
Data Board
Data transferred at full speed for 10k clocks
VME read compare to Simulation
Input Fifos
Software under development
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XTRP Teststand 3 Wilson Hall

• Data Board I
• No more layout errors found
• Data Board Transition Module - new board
  necessary
• wiring corrections 5
• PCB footprint for Muon connector is wrong
• Clock Board
• No more layout errors found
• Clock Board Transition Module - new board
  necessary
• Errors found independent of testing

15
Plan for New Hardware

• Data Board II
• Quotes requested, waiting for responses
• Contract Assembler reviewing BOM
• Target date for 1st DBII April 1, 2000
• Data Board Transition Module
• Want to connect to Muon Calorimetry systems
  first
• Target date for new TM April 15, 2000
• Clock Board Transition Module
• Need a new board for SVT L2P integration
• Target date for new TM May 1, 2000

16
Input Test Error
x000000 to xFFFFFF
Linker(2) Output Formatters
Backplane
Data Board Transition Module
Data Board
3.3V LVDS Receiver
3.3V LVTH Latch
xFFFFEF
Error seen on only 1 out of 96 bits
xFFFFFF