FPGA based triggers

1
FPGA based triggers

• UIUC and PSI built 6 FPGA modules
• 1-2 for master logic
• 2 for FADC trigger
• 2 for eSC gating
• Fred and Peter program them in Verilog HDL.

2
FADC trigger
3
EVH
//mSCgate wire temp3 upgate upg1(mSC,mSCgate_up,c
lk) // updating gate for all
mSC assign temp3 mSC mSCgate_up gg100
gg1(temp3,mSCgate,clk) // start mSCgate
only with no previous PU mSC // NPU signal reg
last always _at_ (posedge clk) // 200 ns pulse
pair resolution for PU begin lastlt
mSCgate // buffer last output if (!mSCgate
!mSCgate_up) // set if mSCgate was 1 last time
and is 0 now mSCNPUlt last else mSCNPUlt
0 end // EVH trigger assign EVH in
mSCgate wire evh2 gg100 g7 (EVH,evh2,clk) assig
n EVHNPU evh2 mSCNPU endmodule
4
EVH
See Peters elog entries
5
EHEH
// program reg clk always _at_ (posedge
clk5) clkclk // 400 ns /2.5 MHz clk // define
mu assign mu in mSCgate gg100 gg4
(mu,mul,clk) // long mu signal to avoid
double counting // NPU signals assign muNPU mul
mSCNPU // coinc with mSCNPU determines
NPU TPC stop prescaler pre1(muNPU, mukNPU) //
Eh-Eh trigger, reduce to 12 4bit groups //
primitive programming because I did not manage
double indexed register wire 112
group parameter ntick4 //
allows ticks up to 15 6 us reg 1ntick tick1
. assign group1 in14
mSCgate assign group2 in58
mSCgate assign group3 in912
mSCgate assign group4 in1316
mSCgate assign group5 in1720
mSCgate assign group6 in2124
mSCgate assign group7 in2528
mSCgate assign group8 in2932
mSCgate assign group9 in3336
mSCgate assign group10 in3740
mSCgate assign group11 in4144
mSCgate assign group12 in4548
mSCgate
parameter t11 //
lt 16 !!! parameter t215 always _at_ (posedge
clk) begin EhEh0 // 1 if(group1) tick1lt0
else tick1lt (tick1 ltt2) ? tick11
t2 if(tick1gtt1 tick1ltt2) begin testlt1
if(group1) EhEh1 else EhEhEhEh
end else testlt0 // 2 wire
eh2 gg100 g7 (EhEh,eh2,clk) //
make long for NPU coinc assign EhEhNPU EhEh
mSCNPU // NPU coinc endmodule
6
EHEH
Triggers still need to be checked, tested
carefully and simulated with real data!