ECE 636 Reconfigurable Computing Lecture 25 Course Wrapup

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ECE 636Reconfigurable ComputingLecture
25Course Wrap-up
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What is Reconfigurable Computing?

• Computation using hardware that can adapt at the
  logic level to solve specific problems
• Why is this interesting?
• Some applications are poorly suited to
  microprocessor.
• VLSI explosion provides increasing resources.
• Hardware/Software
• Relatively new research area.

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Design abstractions
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Processor FPGA
Three possibilities
daughtercard
Proc
FPGA
chip
Backplane bus (e.g. PCI)
1. FPGA serves as coprocessor for data
intensive applications possible project.
FPGA
chip
Proc
2. FPGA serves as embedded computer for low
latency transfer.
Reconfigurable Functional Unit
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Xilinx XC4000 Cell

• 2 4-input look-up tables
• 1 3-input look-up table
• 2 D flip flops

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Xilinx XC4000 Routing
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Actel Programmable Gate Arrays
I/O Buffers, Programming and Test Logic
Rows of programmable logic building
blocks rows of interconnect
I/O Buffers, Programming and Test Logic
Anti-fuse Technology Program Once
I/O Buffers, Programming and Test Logic
Use Anti-fuses to build up long wiring runs
from short segments
I/O Buffers, Programming and Test Logic
Logic Module
Wiring Tracks
8 input, single output combinational logic
blocks FFs constructed from discrete cross
coupled gates
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Altera Max 7000 Macrocell
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Example DPGA Prototype
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FPGA vs. DPGA Compare
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Min-cut bisecting partitioning
B
A
C
D
partition 1
partition 2
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Hill Climbing Algorithms

• To avoid getting trapped in local minima,
  consider hill-climbing approach
• Need to accept worse solutions or make bad
  moves to get global minima.
• Acceptance is probabalistic. Only accept
  cost-increasing moves some of the time.

Cost
Solution space
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Routing Tradeoffs

• Bias router to find first, best route.
• Vary number of node expansions using
• pcosti (1 a) x pcosti-1 ncosti a x disti

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Architectural Limitation

• Routing architecture necessitates domain
  selection.
• Bigger effect for multi-fanout nets

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Two-dimensional Layout

• Control network supports distributed signals.
• Data routed as four-bit values.

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Rapid Datapath

• Segmented linear architecture
• All RAMs and ALUs are pipelined
• Bus connectors also contain registers

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Basic Functional Unit

• Two inputs from adjacent blocks.
• Local memory for instructions, data.

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Chess Interconnect

• More like an FPGA
• Takes advantage of near-neighbor connectivity

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FPICs

• High internal connectivity
• Not always cost effective

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Hierarchical Crossbar

• Full connectivity occurs at top level
• Routing between FPGAs requires determining level
  at which source and destination share an
  ancestor.
• Simplifies routing

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Linear Array

• Current hardware
• Programs implemented as systolic array
• Input key
• Search each RAM bank for sequence

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Emulation Software Steps
Netlist Translation
Technology Mapping
Many of these are dependent on device
interconnect topology
Divide netlist into fixed-sized chunks
Partitioner
Global Placer
Locate an FPGA for a chunk
Global Router
Make connections between devices
FPGA-specific PR
Xilinx PR
FPGA bitstreams
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Simulation Acceleration

• FPGA system takes the place of one portion of
  simulated design
• Inputs transported to FPGA system.
• Outputs returned from FPGA system.

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Network Routing

• FPGAs popular in network hardware
• New protocols implemented directly in silicon
• Easy to upgrade in the field
• Washington University Gigabit Switch (WUGS)
• Switch provides up to 160 Gbps of bandwidth.

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Pyramid Operations

• Gaussian Pyramid
• Down sample image to compress image size for
  communication.
• Average over a set of points to create new point
• Laplacian Pyramid
• Determine error found from Gaussian Pyramid
• Expand contracted picture and compare with
  original

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Gaussian Pyramid Implementation

• Systolic array in which each device performs a
  separate function.
• Limited by clock rate of slowest device.

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Proposed Data Acquisition System
Gigabit Ethernet Interface
64K X 16 DUAL PORT RAM
GIGABIT ETHERNET PHY
RJ45
Radar Control Interface
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36
Hard Disk Interface
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FPGA2 Stratix EP1S40 (Storage Control)
FPGA1 Stratix EP1S40 (Data Processing)
3.3 V BUFFER
Gigabit Ethernet core
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ATA66 IDE Channel 0
3.3 to 5 V BUFFER
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AD6645 (105 MSPS)
H Channel
Analog
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30
30
AD6645 (105 MSPS)
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3.3 to 5 V BUFFER
ATA66 IDE Channel 1
V - Channel
Radar Unit
Analog
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AD974 (200 KSPS)
Radar Positioner Data channel
SRAM 1 x 512K X36 DATA PROCESSING MEMORY
SRAM 3 x 512K X36 DATA PROCESSING MEMORY
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10/100 Mbps Ethernet Interface
16
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ETHERNET PHY
RJ45
MAX 7000A PLD
ATMEL AT91RM9200 MICROCONTROLLER ARM - RISC
CORE (209 MHz 32 BIT)
ETHERNET CONTROLLER
USB INTERFACE
SOFTWARE FLASH 1 X 4M X 16 CONFIGURATION MEMORY
BOOT FLASH 2 X 1M X 16 PROGRAM MEMORY
SDRAM 2 X 8M X 16 DATA MEMORY
USB BLOCK
JTAG PORT
RS232 DRIVER
SERIAL PORT
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Detailed View of Dharma
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Chimaera Architecture

• Live copy of register file values feed into array
• Each row of array may compute from register of
  intermediates
• Tag on array to indicate RFUOP

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Chimaera Architecture

• Array can operate on values as soon as placed in
  register file.
• Logic is combinational
• When RFUOP matches
• Stall until result ready
• Drive result from matching row

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Chimaera Results

• Three Spec92 benchmarks
• Compress 1.11 speedup
• Eqntott 1.8
• Life 2.06
• Small arrays with limited state
• Small speedup
• Perhaps focus on global router rather than local
  optimization.

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Garp

• Integrate as coprocessor
• Similar bandwidth to processor as functional unit
• Own access to memory
• Support multi-cycle operation
• Allow state
• Cycle counter to track operation
• Configuration cache, path to memory

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Garp Array

• Row-oriented logic
• Dedicated path for processor/memory
• Processor does not have to be involved in
  array-memory path

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System Model Adaptive Viterbi Decoder
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Compression Techniques

• Effectively we can consider an FPGA device as a
  collection of cells, each with (x, y) location.
• Instead of using a serial bit stream, could
  consider loading data cell-by-cell like a
  standard memory.
• Specify location of cell through use of two
  registers.

Row
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Hardware Support for Runlength

• Initially latch in base
• Down counter indicates number of strides to take.
• Offset used to augment initial base
• Fairly simple to implement.

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Determining Communication Level
Send, Receive, Wait
Application hardware (custom)
Register reads/writes
I/O driver
Interrupt service
Bus transactions
I/O bus
Interrupts

• Easier to program at application level
• (send, receive, wait) but difficult to predict
• More difficult to specify at low level
• Difficult to extract from program but timing and
  resources easier to predict

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Interface Models

• Synchronization through a FIFO
• FIFO can be implemented either in hardware or in
  software
• Effectively reconfigure hardware (FPGA) to
  allocate buffer space as needed
• Interrupts used for software version of FIFO

r3
p1
p2
p3
r2
d1
FPGA
Control/Data FIFO
d3
d2
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Summary

• Reconfigurable computing relies heavily on new
  VLSI technology
• Device architectures maturing
• Application development progressing at rapid pace
• Integration of hardware and software a difficult
  challenge
• Active area of research at UMass.