Emulator environment based on an FPGA prototyping board

1
Emulator environment based on an FPGA prototyping
board

• Kyung-Soo Oh, Sang-Yong Yoon, Soo-Ik Chae
• School of Electrical Engineering, Seoul National
  University
• Daewoo Electronics, Co.

2
Contents

• Motivation
• Emulator Environment
• Development Flowchart
• FPGA Prototyping Board
• Debug Network
• Virtual Wire
• Automation Program
• Virtual Board
• Test
• Conclusion

3
Motivation

• Target processor Vincent6 (dual)
• DSP for multimedia applications
• Dual processor
• We expanded from 4 FPGA board to 9 FPGA board.
• High speed functional verification of DSP
• Software-based VHDL simulator 100 cycles /s
• FPGA prototyping board 40,000 cycles /s
• Verification of Highly integrated DSP processor
• Use 9 FPGA one FPGA is not sufficient.
• Virtual wire overcome pin limitation between
  FPGA
• Cache and Buffer modeling with SRAM

4
Emulator Environment
FPGA Board
VHDL Library
Vch
ctrl
PCI
ctrl
Debug
Master
Run
Debug
ctrl
Slave
Control Function
Emulator Environment
DownLoad
()
Virtual Board
Debug_read()
Debug_write()
Automation program
EXPAND
PART
VWIRE
virtual board maker
5
Development Flowchart
ORIGINAL.VHD
ORIGINAL.VHD
EXPAND
Partition File Generator
MODIFIED.VHD
EXPANDED.VHD
expanded VHDL file
PART
Partition File Generator
PART0_CORE.VHD
partitioned VHDL file
PART0_CORE.VHD
Virtual Wire Auto Generator
VWIRE
virtual wired VHDL file
PART0.VHD
PART0.VHD
Synthesizer Alliance2.1
Virtual Board Generator
Synthesizer Alliance2.1
Virtual Board Generator
V6BOARD.VHD
PART0.RBT
V6BOARD.VHD
PART0.RBT
Cyclone Simulator
FPGA BOARD(PC)
Emulator
Emulator
Virtual board
FPGA board
6
FPGA Prototyping board
SDRAM
FLASH
FPGA Xilinx XCV1000-BG560 SRAM Samsung
KM736V890(1MB) SDRAM Samsung KM432S2030C(8MB) FL
ASH Samsung KM29U64000T(4MB) PCI PLX
PCI9050-1 Operating Speed Virtual wire
debug network 4 MHz Core
40 KHz
slave6
slave8
slave7
SRAM
SRAM
80
80
80
80
80
slave3
slave4
slave5
SRAM
SRAM
80
80
80
80
80
slave1
master
slave2
SRAM
SRAM
80
80
PC
pci9050
Parallel port
7

• FPGA Board

FPGA Prototyping board(contd)
8
Debug Network

• Overview

9
Debug Network(contd)

• Debug Interface

DMA_CLK(60 KHz)
Debug_Mode When asserted, all pipeline
in target processor is stopped and target
processor is ready to receive command. Debug_Addr
address and debug command. (master
slaves) Debug_Data_In data for write
function. (master
slaves) Debug_Data_Out data for read function.
(slaves master) Core_Clk
clock for target processor. DMA_Clk
clock for direct memory access.
10
Debug Network(contd)

• Basic Function to control board
• Can direct access debug module
• PCIreadData
• PCIreadStatus
• PCIwriteData
• debugRead(int chipId,int debugId,int addr)
• debugWrite(int chipId,int debugId,int addr,int
  data)
• ex) step 3 debugWrite(0,7,0,3)
• Bases of Emulator program

11
Virtual Wire

• To overcome pin limitation
• Increase external signals by time multiplexing
• Comprise of shifter and controller

12
Virtual Wire(contd)

• Partition structure
• Flip-Flop to Combination logic
• Combination logic to Flip-Flop
• Combination logic to combination logic

FPGA CLK
CORE CLK
DEBUG_MODE
VCH_STATE
A1
A0
E1
LD
SHIFT1
A1
A0
A1
E3
LD
E2
SHIFT2
phase 1
phase 2
13
Virtual Wire(contd)

• Estimate virtual wire size
• Maximu interconnection between partitioned blocks
  1876
• Physical wire between FPGAs 80
• Virtual channel per one Physical wire 1876 / 80
  23.45
• But we adapted 30 for flexibility.
• Utilization 24 / 30 100 80
• Estimate core clock period
• Time sharing of cache modeling and virtual
  channel
• Cache and buffer modeling
• required clocks for a buffer 3 clocks
• Maximum buffers allocated to a SRAM 5 ( two
  port buffer)
• required clock for a SRAM 3 5 2 30 clocks
• Virtual wire
• required clocks 30 2(two phase scheme) 60
  clocks
• Core clock period
• 30(buffer modeling) 60(virtual wire) 14(for
  other state) 104 clocks
• 4MHz (FPGA clock) / 104 40 KHz

14
Automation programs

• EXPAND
• expand a block to lower level in VHDL code
• output file is used as input file of Part.
• Part
• make partitioned VHDL codes for each FPGA.
• Vwire
• generate virtual wire for partitioned port.
• insert Debug controller for special debug port.
• This output file is input file of synthesis.

15
Virtual Board

• Verifying the modified vhdl codes and eliminate
  some bugs
• Hardware model, slang function and socket program
• Simulate the virtual board in cyclone with waver

Virtual Board(cyclone)
waver
Kernel
Emulator ver0.5
cmd
gtgt
PCI9050 (slang)
Emulator
Socket
SW
16
Test

• Quick sort
• test for basic instruction
• Adpcm
• test for basic instruction and cache
• G.723 (752 frame)
• 3 hour
• require 10 MHz for real time test
• H.263
• will be tested in July

17
Conclusion

• Implement Emulator Prototype Environment
• 40,000 cycle/s
• contain 9M system gates
• Future Work
• Speed up Core clock
• Do partition to reduce channel between FPGAs
• Solve timing problem such as clock skew and
  critical path