Constructing Current-Based Gate Models Based on Existing Timing Library

1
Constructing Current-Based Gate Models Based on
Existing Timing Library

Andrew Kahng, Bao Liu, Xu Xu UC San
Diego http//vlsicad.ucsd.edu
2
Outline

• Gate Modeling Background
• Problem Formulation
• Approximation and Regression
• Applications
• Experiments
• Conclusion

3
Gate Models

• K-factor lookup tables
• Dg f(Cload, Tr)
• Trout g(Cload, Tr)
• Efficient capacitance Ceff for distributed load
  capacitance
• To achieve identical gate delay (and output
  signal transition time at the same time!)
• E.g., by achieving the same average gate output
  current

4
Calculating Effective Capacitance
Ceff Cload
Trout g(Ceff, Tr)
Ceff s.t.
Iout(Ceff)Iout(load)

1. If (Ceff gt Cload Ceff lt 0)
2. Return Cload
3. Else if(DCeff lt e)
4. Return Ceff
5. Else
6. Continue iteration

• May not converge
• No equivalent gate delay and Trout at the same
  time
• Waveforms are not ramp functions!

5
Current-Based Transistor Model

• MOSFET is a voltage-controlled current source,
  e.g., as in the alpha-power-law model
• For a simple inverter, gate output current is
  given by one of the transistors
• An equivalent inverter macro-model for an
  inverting complex gate
• ? current-based gate modeling

6
Current-Based Gate Modeling

• Consists of a lookup table I(Vi, Vo) and C(Vi,
  Vo)
• Transient analysis for output signal waveform

R
Vo
Vi
Vi
I(Vi, Vo)
C
Voltage-Based
Current-Based
7
Gate Pre-Characterization

• Current-based gate models need additional
  pre-characterization, e.g., I(Vi, Vo), given by
  SPICE DC sweep analysis
• Cadence Effective Current Source Model (ECSM)
• Synopsys Composite Current Source Model (CCS)

Rise_transition (template) index_1 // slew
rate index_2 // load cap values //
output Tr ecsm_waveform (name1)
index_3 // output voltage values //
time point
8
Outline

• Gate Modeling Background
• Problem Formulation
• Approximation and Regression
• Applications
• Experiments
• Conclusion

9
Constructing Current-Based Gate Model From
Existing Timing Libraries

• Given gate delays and output slew rates for load
  caps and input slew rates, find an equivalent
  current-based gate model, e.g., I(Vi, Vo) and C

Vi
I(Vi, Vo)

• Dg f(Cload, Tr)
• Trout g(Cload, Tr)

Tr
Dg
C
Cload
Vo
I
Tr
Trout
C
Vi
Cload
10
Inverse Problem

• To find an unknown underlying physical process by
  a set of measurements
• Q C V
• Inhomogeneous Fredholm integral equations of the
  first kind

11
Solving an Inverse Problem

• Integral equations ? differential equations
• Apply interpolation to reduce variables to those
  in the I(Vi, Vo) lookup table
• Inverse problem solutions are extremely sensitive
  to input data perturbations!
• Inverse problem ? Optimization w/ objective A a
  S (A accuracy, S smoothness, a weighting
  factor)

12
Outline

• Gate Modeling Background
• Problem Formulation
• Solution Approximation and Regression
• Applications
• Experiments
• Conclusion

13
Polynomial Regression of I(Vi,Vo)

• A priori knowledge
• Approximate I(Vi, Vo) by a quadratic polynomial
• 91 coefficients in a limited range

14
Polynomial Regression of I(Vi,Vo)
15
Our Constructive Method

• Start with an initial polynomial coefficient
• For each iteration
• Perturb a coefficient ai ai d
• Compute mean square gate delay mismatch e
• If e reduces, commit perturbation ai ai d
• Else, go other direction ai ai d
• Stop if no improvement
• Reduce step d for another iteration
• Compute I(Vi, Vo) and C

16
Applications

• More accuracy, arbitrary waveform
• Efficiency advantage over SPICE simulation
• Gate delay calculation for
• Long interconnects
• Cross-coupling interconnects
• Supply voltage drop effect
• Supply current calculation
• Noise calculation

17
Supply Voltage Variation Effect on Gate Delay
Calculation

• There exists an equivalent inverter macro-model
  for each input combination for any (inverting)
  complex gate
• Adjust input and output voltages for I(Vi, Vo)
  table lookup for a falling input signal, but not
  for a rising input signal

18
Experiments

• BPTM 70nm technology cell library
• Compare (our) constructed and (SPICE simulation
  based) pre-characterization models

Our Constructed Our Constructed Quad. Pre -Characterization Quad. Pre -Characterization Cubic Pre -Characterization Cubic Pre -Characterization
m s m s m s
invx4 1.25 5.7 9.73 45.2 11.12 37.8
invx8 1.85 16.9 12.93 27.2 14.67 27.8
nor2x4 0.46 4.8 7.06 152.7 5.91 56.5
19
Experiments

• Gate delays by (1) our model and (2)
  pre-characterized model normalized by SPICE
  simulation results

For Ideal (1.0V) Supply Voltage For Ideal (1.0V) Supply Voltage For Ideal (1.0V) Supply Voltage For Ideal (1.0V) Supply Voltage For Ideal (1.0V) Supply Voltage For Ideal (1.0V) Supply Voltage For Ideal (1.0V) Supply Voltage For Ideal (1.0V) Supply Voltage For Ideal (1.0V) Supply Voltage
(1) 93.0 97.4 99.0 101.0 97.8 94.9 95.7 98.0
(2) 100.0 98.7 99.3 100.0 102.5 101.2 100.6 100.0
(1) 98.4 102.6 99.0 95.5 103.9 100.8 100.2 99.5
(2) 104.3 101.8 100.0 100.0 97.6 98.5 99.2 100.1
For Degraded (0.9V) Supply Voltage For Degraded (0.9V) Supply Voltage For Degraded (0.9V) Supply Voltage For Degraded (0.9V) Supply Voltage For Degraded (0.9V) Supply Voltage For Degraded (0.9V) Supply Voltage For Degraded (0.9V) Supply Voltage For Degraded (0.9V) Supply Voltage For Degraded (0.9V) Supply Voltage
(1) 102.0 105.4 106.7 108.6 101.2 106.8 108.6 106.9
(2) 102.1 99.8 98.7 98.8 100.8 99.6 98.7 97.9
(1) 107.8 106.4 106.6 106.2 107.8 106.4 106.6 108.3
(2) 100.0 99.6 99.1 97.8 95.6 97.9 98.7 100.2
20
Summary

• Utilize existing timing libraries for application
  of novel current-based gate modeling
• Wide range of applications supply current
  calculation, delay calculation for complex
  waveforms, e.g., resistive shielding, crosstalk
  coupling, supply voltage variation, etc.
• Slightly less accurate than pre-characterized
  current-based gate models, e.g., within 8.6 vs.
  4.4 for gate delay calculation with varied
  supply voltage
• Reasonable runtime for model construction, 28.3
  seconds in average on a 2.8GHz P4 system

21
Thank you !