HIAPER Cloud Radar HCR Preliminary Design Review 81806

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Signal Processing

• Use FPGA based commercial (COTS) digital receiver
  waveform generator
• Sub-sample 125 MHz IF _at_ 100 MHz
• Leverage digtal down converter (DDC) currently
  under development in EOL software defined radio
  (SDR) initiative
• Generate 125 MHz quadrature waveforms required
  for exciter
• Send raw I,Q data to in-cabin processor via
  Ethernet
• Anticipated data rate 128 Mbits/sec (raw I,Q) or
  58 GB/hr
• Perform spectral processing on all range gates
• Single 3.6 GHz Pentium 4 should be sufficient
  based on fftw3 benchmark _at_ 20 efficiency (1024
  point FFT, 500 range gates, 102.4 msec dwell)
• Generate, display and record moments from
  spectra
• Record limited quantities of timeseries data,
  disk space a limiting factor