Semiconductors: What Lies Ahead

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Semiconductors What Lies Ahead?

• Ralph K. Cavin, III
• NEEDHA Annual Meeting
• March 18, 2000
• New Orleans, LA

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Outline

• A Vision for Century 21
• The 1999 International Technology Roadmap for
  Semiconductors (ITRS) Messages?
• The Red Brick Wall
• Future of MOS technology?
• Physics How different at the nanoscale?
• From continuum to atomic models
• Thoughts on technology directions
• SIA Initiative
• Conclusions

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A Vision of Life in the 21st Century

• Every person has easy access to all the
  accumulated knowledge of the human race.
• Any time, any place, any format, any language
• Every person can interact with any other or every
  other human being any place, any time.
• Virtual commerce through cashless, paperless
  transactions
• Virtual transportation and intelligent highways
• Limitless individual and public entertainment
  options
• Every person has access to comfort, dignity and
  health
• Design/manufacturing for a sustainable planet
• Abundant, clean, safe, affordable energy
• Reliable, cost effective medical diagnostics and
  prostheses
• IEEE http//www.ieee.org/tab/grandchal.html

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Megatrends in Information Technology (IT)

• Major Revolution in IT Use Continues
• Internet grows at 20 per month
• Software Life Cycle shrinks from 13 years to 4
  years
• Seamless integration of wireless wired
  communications
• Mobile applications electronic commerce grow
  exponentially
• Information Technology Becomes Ubiquitous
• Private life (reaches all economic levels)
• Business (11 of sales in 2001 vs. 3.5 in mid
  90s)
• Global (expands into all the developing
  countries)
• Quality of Life Improvement
• Smart appliances, cars, highways and buildings
• Easier access to all knowledge
• Revolutionary new concepts in health-related
  fields

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Technology Enablers for New Applications
Bio-electric computers
Quantum computers Molecular electronics
True neural computing for Intelligent
communicators, controllers, assistants
Smart lab-on-a-chip Plastic/Printed
ICs Self-assembly
106-107-x lower power for lifetime
micro-batteries
Vertical/3D CMOS Micro-wireless nets Integrated
Optics
Wearable communicators, Wireless remote
medicine, Hardware over the Internet
Metal gates Hi-k/metal oxides Low-k w/. Cu SOI
Pervasive voice recognition, Smart
transportation, etc.
Full motion mobile video, Fully integrated mobile
office
Now 2 4 6 8 10 12 14 16 years
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The Red Brick Wall Forecast by ITRS 99

• Upcoming Technology Barriers (Some within 6
  years)
• Scaling SiO2 gate dielectrics
• Doping limits in silicon and polysilicon
• Ion implantation limits
• VT scaling limits
• Bulk CMOS structure limits
• End of metal-dielectric interconnect progress
• Package I/O limits
• Tyranny of low cost, error free manufacturing
• Efficient design of systems with billions of
  imperfect and interacting components

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Approaching a Red Brick WallChallenges/Opportun
ities for Semiconductor RD
Year of Production 1999 2002 2005
2008 2011 2014 DRAM Half-Pitch nm 180
130 100 70 50 35 Overlay Accuracy nm
65 45 35 25 20 15 MPU Gate Length nm
140 85-90 65 45 30-32 20-22 CD Control
nm 14 9 6 4 3 2 TOX (equivalent)
nm 1.9-2.5 1.5-1.9 1.0-1.5 0.8-1.2
0.6-0.8 0.5-0.6 Junction Depth nm 42-70
25-43 20-33 16-26 11-19 8-13 Metal Cladding
nm 17 13 10 0 0 0 Inter-Metal
Dielectric K 3.5-4.0 2.7-3.5 1.6-2.2
1.5 lt1.5 lt1.5
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Interconnections
Low K
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Gate Dielectric Scaling(ITRS 1999)
2.4
1.8
Tox equivalent (nm)
1.2
0.6
4
8
0
6
2
Monolayers
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Advanced CMOS Contact Structure at 50 nm
Metal Gate
1 dopant
metal
n Si-Ge
45 atoms
100 atoms
New Gate Dielectric
n
45 atoms
1 dopant
substrate
S/D Contact
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Design is hard
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(Interconnect is one of many design problems.)
Design Complexity
Superexponential
Functionality Testability Functionality
Testability Wire Delay Functionality
Testability Wire Delay Power Mgmt
Functionality Testability Wire Delay Power
Mgmt Embedded software Functionality
Testability Wire Delay Power Mgmt Embedded
software Signal Integrity Functionality
Testability Wire Delay Power Mgmt Embedded
software Signal Integrity Hybrid
Chips Functionality Testability Wire Delay
Power Mgmt Embedded software Signal Integrity
Hybrid Chips RF Functionality Testability
Wire Delay Power Mgmt Embedded software
Signal Integrity Hybrid Chips RF
Packaging Functionality Testability Wire
Delay Power Mgmt Embedded software Signal
Integrity Hybrid Chips RF Packaging Mgmt
of Physical Limits

• In short
• Technology hardness scales with critical
  dimension and number of levels
• Design hardness scales with the number of elements

• Exponentially growing number of elements
  (devices wires)
• Design complexity is exponential function of
  element count

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The Design Tool Environment

• Design productivity requires higher levels of
  design
• design re-use
• high-level synthesis
• system-level verification
• specialized tools operating at structured levels
• . . .

• Product functionality and performance require
  interacting tools reaching from high to circuit
  level
• synthesis/verification/PD together
• dynamic logic families
• critical timing behavior
• interconnect-aware design
• SoC with digital/analog/memory/software
• . . .

W.Joyner, SRC, Feb2000
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CMOS Future Directions and Beyond
70/2-3year
Features
70 / 2-3year
2X Performance/2-3year
??/2-3year
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The Vertical Replacement-Gate (VRG) MOSFET
Combines the advantages of previous vertical
MOSFETs with the essential features of planar
MOSFETs
VRG-MOSFET
Planar MOSFET
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FinFET Body is a thin silicon Fin

• Double-gate structure thin body
• Raised Source/Drain

Source
Drain
Gate
Source
Drain
Si fin - Body!
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Nano-devices Time-scale(May be occurring sooner
than expected)
Molecules
Atoms
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Traditional Cornerstones of MOSFET Device Physics

• MOSFET structure design
• Short channel effects
• Electric field distributions in channel and
  source/drain
• Equilibrium bulk and interface properties of
  materials (Si and SiO2) determine MOSFET
  performance transient charge carrier transport
  (e.g. ballistic) has not been important
• Materials engineering used to define MOSFET
  structure
• Materials choices (gate electrode, gate
  insulator, channel, dopant specie and
  distributions)
• Gate oxide/semiconductor interface control
  engineering
• Models/simulators used to understand/engineer
  MOSFETs
• Statistical distributions are assumed adequate
  for charge carriers
• Continuum models (2D) have been assumed quantum
  effects have not been important

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Emerging Nanoscale Semiconductor Physics Phenomena

• 1. Microscale to nanoscale dimensions
• 2. effect
• 2. Single dopant effects
• 3. Surface /Interface dominance
• 4. Interface-to interface interactions in
  nano-scale devices
• 5. Materials fabrication
• Reaction kinetics
• Defect tolerance
• Super-molecules
• 6. Non - periodicity effects
• 7. High field effects
• 8. Single particle transport phenomena

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Semiconductor structures as Supermolecules

• It would be, in principle, possible for a
  physicist to synthesize any chemical substance
  that the chemist writes down. Give the orders and
  the physicist synthesizes it. How? Put the atoms
  down where the chemist says.
• Richard Feynmann, 1959
• As features continue to shrink towards the
  nanometer domain, a bottoms-up chemical
  perspective of engineering molecular
  architectures and correlating precise molecular
  components with device function will offer new
  insights into fundamental semiconductor dynamics,
  facilitate cost effective manufacturing, and
  stimulate new possibilities.

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Bizarre Quantum World
Which path is taken?
BOTH
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Quantum superpositions
Quantum computers operate on superpositions of
logical states
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The Economy, Federal Research, the
Semiconductor IndustryAn SIA Initiative

• The economy and funding of basic research show
  positive signs of health
• However, the private sector funds 2/3 of RD
  while the government funds 1/3 of RD
• A major shift in RD support has occurred
• Ramifications are
• Basic research shrinking
• Narrower set of research options supported
• Private RD vulnerable to economic cycles
• Serious concern is that the funding for physical
  science and engineering is declining.

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The Economy, Federal Research, the
Semiconductor Industry

• Many of the G7 countries spend more of their GDP
  on RD than the US
• More countries are acquiring the capability to
  innovate at the state of the art
• Semiconductor industry needs a continuing supply
  of technical talent
• Negative impact due to declining RD budgets
• More foreign students are returning to their home
  countries
• The industry faces, within 6 years, many
  technical problems for which there are no known
  solutions

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The Economy, Federal Research, the
Semiconductor Industry

• Recommendations
• SIA to stimulate/participate in federal RD
  strategy to increase support for basic research
  in physical sciences engineering
• Develop cooperative industry efforts that
  leverage federal RD efforts and through it
  enhance government, university and industry
  partnerships
• Focus on attracting more U.S. students to the
  physical sciences and engineering in order to
  enhance the professional and technical workforce

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The Economy, Federal Research, the
Semiconductor Industry

• Recommendations
• Together with the federal government assure that
  the infrastructure of government and university
  laboratories in equipment and capabilities to
  support forefront research in the physical
  sciences is maintained.

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Conclusions

• Never before have we faced such a combination of
  technical challenges and opportunities
• Keep MOS scaling going to its ultimate limit
• Transition from continuum to atomic understanding
• Invent new technologies at the granularity of
  matter to sustain Moores law benefits to society
• Only a joint and focused effort by government and
  industry can preserve our momentum
• Universities must play a much more critical role
  in discovery research and will become a key
  factor for success

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Questions

• Can we as Electrical Engineering educators
• Prepare students for creativity across the
  spectrum from atomic level at one extreme to
  intelligent machine architectures at the other?
• Can/should universities conduct an increasing
  share of basic research for future industrial
  technologies?
• What are the success factors?
• Will these results come from EE departments?
• How can we entice more students to pursue careers
  in semiconductor technology-related fields?

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Acknowledgements

• Many people have contributed to the material used
  in this paper
• Erich Bloch - Washington Advisory Group
• Kathleen Kingscott - IBM
• Bob Doering - TI
• Paolo Gargini - Intel
• Jim Hutchby, Harold Hosack, Daniel Herr, Victor
  Zhirnov, Lawrence Arledge, Bill Joyner, all of
  SRC
• Juri Matisoo - SIA
• John Candelaria - Motorola
• Hundreds of ITRS 99 contributors

SRC/File name/ 40