CPE 431531 Chapter 5 The Processor: Datapath and Control

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CPE 431/531Chapter 5 - The Processor Datapath
and Control
Swathi T. Gurumani Modified From Slides of Dr.
Rhonda Kay Gaede UAH
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• HW4 5.1, 5.2, 5.8, 5.10, 5.14
• Due October 2nd (Monday)
• Solution before the exam

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5.4 A Simple Implementation Scheme - Adding a
Control Unit
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5.4 A Simple Implementation Scheme - R-type
Instruction Execution
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5.4 A Simple Implementation Scheme - lw
Instruction Execution
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5.4 A Simple Implementation Scheme beq
Instruction Execution
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5.3 A Simple Implementation Scheme Implementing
Jumps
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5.4 A Simple Implementation Scheme - j
Instruction Execution
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5.4 A Simple Implementation Scheme - R-type
Instruction Timing
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5.4 A Simple Implementation Scheme - lw
Instruction Timing
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5.4 A Simple Implementation Scheme - sw
Instruction Timing
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5.4 A Simple Implementation Scheme - beq
Instruction Timing
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5.4 A Simple Implementation Scheme - j
Instruction Timing
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5.4 A Simple Implementation Scheme -
Performance Considerations

• The clock cycle is determined by the longest
  possible path in the machine.
• For this MIPS implementation, this happens with a
  instruction.
• Given
• operation times of
• 200 ps - memory units
• 100 ps - ALUs and adders
• 50 ps - register file read or write
• 0 ps - multiplexors, control unit, PC access,
  sign-extension, wires
• Instruction mix
• 25 loads
• 10 stores
• 45 R-format
• 15 branches
• 5 jumps

lw
Pg. 315 Example
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5.4 A Simple Implementation Scheme -
Performance Considerations

• Which is faster and by how much?
• Implementation with fixed clock cycle
• Implementation with variable clock cycle

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5.9 Real Stuff The Organization of Recent
Pentium Implementations

• Pipelining improves performance by overlapping
  the execution of multiple instructions.
• The last Intel processor without pipelining was
  the 80386 introduced in 1985 the very first MIPS
  processor, the R2000, also introduced in 1985,
  was pipelined.
• Hardwired Control Implementation of FSM
• Microcode set of microinstructions that control
  a processor
• Microinstruction Representation of control using
  low-level instructions, each of which asserts a
  set of control signals

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5.9 Real Stuff The Organization of Recent
Pentium Implementations

• Every Intel implementation of the 80x86
  architecture since the 486 has used a combination
  of hardwired control to handle simple
  instructions, and microprogrammed control to
  handle the more complex instructions.
• Superscalar Enables the processor to execute
  more than one instruction per clock cycle
• Micro-operations (Intel terminology) RISC-like
  instructions directly executed by the hardware

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5.9 Real Stuff The Organization of Recent
Pentium Implementations Pentium 4

• Recent Pentium processors are capable of
  executing more than one instruction per clock
  (superscalar). The processor has multiple
  datapaths.
• The Pentium III and 4 allow up to three IA-32
  instructions to execute in a clock cycle
• They execute simple micro-operations which are
  fully self-contained operations that are
  initially about 70 bits wide.They trigger control
  that is completely hardwired - 120 for the
  integer datapath and 275-400 for the
  floating-point datapath

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5.7 Real Stuff Translation from IA-32
Instructions to Micro-operations

• Pentium III instruction decode would look up to
  3 instructions at a time and use PLAs to generate
  up to 6 micro-operations
• Pentium 4 Use a trace cache
• Translation is in trace cache, fetch
  micro-operations
• Translation is in trace cache and requires more
  than four micro-operations, transfer control to
  microcode ROM
• Translation is not in trace cache, decode
• If fewer than four micro-operations, place in
  trace cache
• Otherwise, use microcode ROM to complete

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5.9 Concluding Remarks

• Control is one of the most challenging aspects of
  computer design.
• Understanding of how all the components in the
  processor operate
• Abstraction is used to specify control.
• We move from specification to implementation.