332:479 Concepts in VLSI Design Lecture 26 Pads

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332479 Concepts in VLSIDesignLecture 26Pads

• Pad frames
• Output pads
• Input pads
• Bidirectional pads
• Miscellaneous pads
• Summary

• Michael L. Bushnell and David Harris
• Rutgers University and Harvey Mudd College

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Material from Principles of CMOS VLSI Design By
Neil E. Weste and Kamran Eshraghian
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Input/Output Structures

• Requires the most circuit design expertise and
  detailed process knowledge
• Pad size 100 to 150 mm2
• Pad spacing minimum pitch at which bonding
  machines can operate 150 to 200 mm

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Interdigitated (a), Core-limited (b) or
Pad-limited (c) Pads
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Bump Pad

• Can be put anywhere on chip
• Plate pads with solder bumps
• Invert chip reflow bond to substrate
• Invented by IBM
• No pad connection failure EVER in IBM equipment

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Pad Design

• Use multiple power ground pads to reduce noise
• Place VSS as outermost track

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Pad Design
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Example Pad Frame

• VDD / VSS Crossover

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Input / Output

• Input/Output System functions
• Communicate between chip and external world
• Drive large capacitance off chip
• Operate at compatible voltage levels
• Provide adequate bandwidth
• Limit slew rates to control di/dt noise
• Protect chip against electrostatic discharge
• Use small number of pins (low cost)

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I/O Pad Design

• Pad types
• VDD / GND
• Output
• Input
• Bidirectional
• Analog

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Output Pads

• Drive large off-chip loads (2 50 pF)
• With suitable rise/fall times
• Requires chain of successively larger buffers
• Guard rings to protect against latchup
• Noise below GND injects charge into substrate
• Large nMOS output transistor
• p inner guard ring
• n outer guard ring
• In n-well

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Input Pads

• Level conversion
• Higher or lower off-chip V
• May need thick oxide gates
• Noise filtering
• Schmitt trigger
• Hysteresis changes VIH, VIL
• Protection against electrostatic discharge

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ESD Protection

• Static electricity builds up on your body
• Shock delivered to a chip can fry thin gates
• Must dissipate this energy in protection circuits
  before it reaches the gates
• ESD protection circuits
• Current limiting resistor
• Diode clamps
• ESD testing
• Human body model
• Views human as charged capacitor

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Bidirectional Pads

• Combine input and output pad
• Need tristate driver on output
• Use enable signal to set direction
• Optimized tristate avoids huge series transistors

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Analog Pads

• Pass analog voltages directly in or out of chip
• No buffering
• Protection circuits must not distort voltages

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MOSIS I/O Pad

• 1.6 mm two-metal process
• Protection resistors
• Protection diodes
• Guard rings
• Field oxide clamps

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Output Pad Design Constraints

• Latchup most apt to happen in pads
• Separate n and p transistors
• Use guard rings tied to supply
• Use double guard rings on I/O transistors
• Surround n transistor with VSS p ring
• Surround p transistor with VDD n ring
• Make rings continuous in diffusion and strapped
  with metal
• Use dummy collectors between I/O transistors and
  internal circuitry
• p connections to VSS
• n (in n-well) connections to VDD

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More Pad Design Constraints

• Connect I/O transistors to dirty VSS VDD supply
  signals
• Single point connect to dirty VSS VDD
• All VSS / VDD connections must be ohmic in
  metal
• Make I/O transistors from parallel smaller
  transistors
• CMOS driver transistors are usually capable of
  sinking 1.6 mA for a standard TTL load with VOL lt
  0.4 V

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Input Pads

• CMOS gate oxide punctures breaks down at 40 to
  100 V
• Use combination of resistance Zener diode
  clamps to prevent this voltage from building on
  gates
• Typical circuit
• R limits diode peak current
• 200 W R 3 kW
• Use a tub resistor p diffusion in an n-well
  process
• Clamping diodes n in substrate and p in n-well
• Diodes need double guard rings

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Input Pads
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Input Pad Layout
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n-Well Process Pads

• Can use all n-device I/O circuitry
• n diffused protection resistors
• n punchthrough devices
• Closely spaced source drain diffusion but no
  gate
• Avalanches at 50 V
• Input buffer longer than normal gates to
  improve breakdown behavior
• Add enough stages to amplify to drive internal
  load

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TTL to CMOS Level Conversion

• When reading TTL inputs into CMOS chip
• Set switching of I/P inverter to
• VOL VOH 0.4 2.4 1.4 V
• 2 2
• Change inverter b ratio
• Use on-chip p transistor tied to VDD (with
  grounded gate) to pull pad input up to VDD when
  it is high

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Clock Buffer Design

• Single driver
• Four-sided approach

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Down-the-Center Approach

• 10 inch long, O/P p transistor for clock driver
  (serpentine)

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Tri-State and Bidirectional Pad
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Bidirectional Pad
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Miscellaneous Pads

• With extra p or n transistor for pull-up or
  pull-down
• With latches or registers
• Gives chip low setup hold times
• Pad does not have to drive the input into the
  chip to internal storage
• Instead latch signal at pad, drive internal
  chip circuits from latch

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Pad Interference

• Fast-rising chip outputs generate UHF frequencies
  interfere with radios, cellular telephones TV
• Control by reducing high-order harmonics
• Controlled slew-rate pads
• Reduce I/O logic swing to reduce harmonics

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CMOS Schmitt Trigger Pad

• Use hysteresis to get a clean edge from a slowly
  varying input

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Summary

• Pad frames
• Output pads
• Input pads
• Bidirectional pads
• Miscellaneous pads