GCD-1

1

• GCD A simple example to introduce Bluespec
• Arvind
• Computer Science Artificial Intelligence Lab
• Massachusetts Institute of Technology

2
Programming withrules A simple example

• Euclids algorithm for computing the Greatest
  Common Divisor (GCD)
• 15 6
• 9 6 subtract
• 3 6 subtract
• 6 3 swap
• 3 3 subtract
• 0 3 subtract

answer
3
GCD in BSV
module mkGCD (I_GCD) Reg(int) x lt- mkRegU
Reg(int) y lt- mkReg(0) rule swap
((x gt y) (y ! 0)) x lt y y lt x
endrule rule subtract ((x lt y) (y !
0)) y lt y x endrule method
Action start(int a, int b) if (y0) x lt a y
lt b endmethod method int result() if
(y0) return x endmethod endmodule
typedef int Int(32)
Assumes x / 0 and y / 0
4
GCD Hardware Module
In a GCD call t could be Int(32), UInt(16), Int
(13), ...
implicit conditions
interface I_GCD method Action start (int a,
int b) method int result() endinterface

• The module can easily be made polymorphic

• Many different implementations can provide the
  same interface module mkGCD (I_GCD)

5
GCD Another implementation
module mkGCD (I_GCD) Reg(int) x lt- mkRegU
Reg(int) y lt- mkReg(0) rule
swapANDsub ((x gt y) (y ! 0)) x lt
y y lt x - y endrule rule subtract
((xlty) (y!0)) y lt y x
endrule method Action start(int a, int b) if
(y0) x lt a y lt b endmethod
method int result() if (y0) return x
endmethod endmodule
Does it compute faster ?
6
Bluespec Tool flow
Bluespec SystemVerilog source
Bluespec Compiler
Verilog 95 RTL
Verilog sim
VCD output
Debussy Visualization

• Place
• Route

• Physical

• Tapeout

7
Generated Verilog RTL GCD
module mkGCD(CLK,RST_N,start_a,start_b,EN_start,RD
Y_start, result,RDY_result) input CLK
input RST_N // action method start input 31
0 start_a input 31 0 start_b input
EN_start output RDY_start // value method
result output 31 0 result output
RDY_result // register x and y reg 31 0
x wire 31 0 xD_IN wire xEN reg 31
0 y wire 31 0 yD_IN wire yEN ... //
rule RL_subtract assign WILL_FIRE_RL_subtract
x_SLE_y___d3 !y_EQ_0___d10 // rule RL_swap
assign WILL_FIRE_RL_swap !x_SLE_y___d3
!y_EQ_0___d10 ...
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Generated Hardware
x_en y_en
swap?
swap? OR subtract?
9
Generated Hardware Module
start_en
sub
x_en swap? y_en swap? OR subtract?
OR start_en
OR start_en
rdy
(y0)
10
GCD A Simple Test Bench
module mkTest () Reg(int) state lt- mkReg(0)
I_GCD gcd lt- mkGCD() rule go (state
0) gcd.start (423, 142) state lt 1
endrule rule finish (state 1) display
(GCD of 423 142 d,gcd.result()) state
lt 2 endrule endmodule
Why do we need the state variable?
11
GCD Test Bench
module mkTest () Reg(int) state lt-
mkReg(0) Reg(Int(4)) c1 lt- mkReg(1)
Reg(Int(7)) c2 lt- mkReg(1) I_GCD gcd
lt- mkGCD() rule req (state0)
gcd.start(signExtend(c1), signExtend(c2))
state lt 1 endrule rule resp (state1)
display (GCD of d d d, c1, c2,
gcd.result()) if (c17) begin c1 lt 1 c2
lt c21 state lt 0 end else c1
lt c11 if (c2 63) state lt 2
endrule endmodule
Feeds all pairs (c1,c2) 1 lt c1 lt 7 1 lt c2 lt
15 to GCD
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GCD Synthesis results

• Original (16 bits)
• Clock Period 1.6 ns
• Area 4240 mm2
• Unrolled (16 bits)
• Clock Period 1.65ns
• Area 5944 mm2
• Unrolled takes 31 fewer cycles on the testbench

13
Exercise Binary Multiplier

• Simple binary multiplication

What does it look like in Bluespec?
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Multiplier in Bluespec
module mkMult (I_mult) Reg(Int(32)) product
lt- mkReg(0) Reg(Int(16)) d lt-
mkReg(0) Reg(Int(16)) r lt- mkReg(0)
rule cycle endrule method Action
start endmethod method Int(32) result ()
endmethod endmodule
rule cycle (r ! 0) if (r0 1) product lt
product d d lt d ltlt 1 r lt r gtgt
1 endrule
method Action start (Int(16)x,Int(16)y) if (r
0) d lt signExtend(x) r lt y endmethod
method Int(32) result () if (r 0) return
product endmethod
What is the interface I_mult ?