SUIF IRs

1
SUIF IRs

• Basant K. Dwivedi

2
Outline

• Introduction
• User requirements
• SUIF1
• SUIF2
• MachSUIF

3
Introduction
4
User Requirements

• Efficient traversal of the IR
• Efficient communication among compiler passes
• code transformations
• annotations
• Availability of libraries for common operations
  such as dataflow analysis
• Flexibility to add
• new IR nodes
• new passes

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SUIF1

• Hierarchical data structure
• If-then-else node
• For-loop node
• Do-while node
• Block node
• Instruction nodes which are expression trees
• Opcodes of instructions resemble RISC
  instructions with exceptions
• mbr multiway branch
• array computes the address of an element in an
  array

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SUIF1 (cont.)

• Code transformations such as
• Dismantling
• Code motion of loop-invariant
• Hoisting of if node
• Control structure simplification
• removal of not taken branches
• Classical optimizations
• common sub-expression elimination
• constant propagation
• dead-code elimination
• A parallelizing compiler is also available.

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SUIF2 Objectives

• Compose compiler with existing passes
• Front ends passes
• Easy expression of compiler compositions
  (dynamically)
• Develop new passes
• User concentrates on algorithmic issues
• Infrastructure takes care of common
  functionalities
• Standard intermediate representation and
  associate tools
• Common utilities and data structures
• Develop new IR nodes
• Easy definition of IR nodes
• Old code works with new IR without recompilation

Source SUIF2 tutorial
8
SUIF2 (cont.)

• SUIF1 system
• Each pass is an independent program that
  reads/writes SUIF in a file
• Advantages modular, visibility of intermediate
  results
• Disadvantages expensive disk access
• SUIF2 system
• write code once, can run on program on disk or in
  memory
• simple development, efficient deployment
• How?
• A pass a common driver module
• A compound pass
• a common driver series of modules loaded
  dynamically

Source SUIF2 tutorial
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Modular Compiler System
COMPILER
A series of stand-alone programs
A driver that imports applies modules to
program in memory
Suif-file1
Suif-file1
drivermodule1
Suif-file2
Source SUIF2 tutorial
Suifdriver imports/executes module1 module2
module3
drivermodule2
Suif-file3
drivermodule3
Suif-file4
Suif-file4
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SUIF2 IR Design

• Root Object
• Uniform functionality
• Fields accessed with get_ltfieldgt, and set_ltfieldgt
• printing
• I/O to disk
• cloning
• iterators
• walkers
• Memory management aid
• object creation via factories
• owner edges embed a tree into program
  representation

Source SUIF2 tutorial
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SUIF1 vs SUIF2

• SUIF1 supports C, fortran
• SUIF2 supports C, fortran, JAVA
• There are no instructions in SUIF2. It has
• Statements if statement, do-while statement
  etc.
• Expressions unary expressions, binary
  expressions etc.
• No definition of semantics of operations such as
  add, sub in SUIF2

SUIF2 file
SUIF1 file
Suif2toSuif1 Converter
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MachSUIF

• Provides libraries to write back-end for a new
  target machine
• Interface for target specific code generation
• Register allocation
• Scheduling
• Uses SUIF2 hoof system to define new IR nodes
• Instruction list
• Instructions
• Operands
• Control flow graph nodes
• Static single assignment form

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Overall flow in MachSUIF
Target specialization passes are parameterized
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SuifVm

• This is the target of SUIF2 lowering passes
• IR nodes are instructions with RISC like opcodes
• mov, load, store etc.
• unlike SUIF1 doesnt have array instruction

Target machine
SUIF2 lowering passes
SuifVm
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Machine Context

• An interface to access target specific
  information employing
• Set of global functions to access target details
  e.g
• is_move is current instruction a move
• reg_caller_saves set of registers to be saved
  by function caller
• MachineContext class to bind target details with
  the global functions dynamically
• Stages
• read target_lib annotation
• find the target context
• register and dynamically load target lib

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Target Machine Instructions

• Opcode specification
• Opcode enumeration
• Filling of functions such as
• opcode_name
• opcode_move
• Query for instruction type
• only required for some specific instructions such
  as
• is_move
• is_call
• reads_memory
• writes_memory

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Translation to the Target Machine

• Functions to translate every suifvm instruction
  should be filled.
• Some suifvm instructions may not occur because of
  preprocessing
• One-to-one mapping for many instructions such as
• add, sub, mul
• Some instructions require more careful
  translation e.g.
• call and return
• type conversion
• structural load and store

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Register file Information

• Specifications is required for
• Number of registers
• Register classes
• Register widths
• Set of allocable registers
• Set of registers in caller save convention
• Set of registers in callee save convention
• Sequence of instructions required for spill

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Register Allocation

• Uses interface functions to access register file
  information
• Pre-scheduling graph coloring register allocator
  called iterated register coalescing
• Tries to reduce
• copy instructions
• spills

Ref George and Appel, TOLPLAS 1996
Register allocation
Code finalize pass
Code-gen
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Scheduling Resource model and Collision matrices
Resources a, b, c Vectors a i1 b
i2 ac, c i3
Ref Bala and Rubin
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Generated Automata
F1
b
x 0 0 0 x 0
F0
a
0 0 0 0 0 0
a
F2
F0 and F4 are Cycle advancing states
b
0 0 x 0 0 0
a
c
c
F3
x 0 0 0 x x
F4
0 0 0 0 x 0
b
F5
b
a
0 0 x 0 x 0
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Libraries in MachSUIF

• Control flow graph library
• Control flow analysis library
• Supports natural loop analysis
• Data flow analyzer library used for
• Liveness information
• Definition-usage info
• Static single assignment (SSA) library for
• ssa based optimizations

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References

• SUIF2 documentation
• MACHSUIF documentation
• Instruction scheduling library for SUIF by Gang
  Chen and Cliff Young, Harvard University
• Efficient instruction scheduling using finite
  state automata by Vasanth Bala and Norman Rubin