The CMOS inverter

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The CMOS inverter
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The CMOS inverter
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The CMOS inverter

Regions of operation (balanced inverter)
Vin n-MOS p-MOS Vout 0 cut-off linear Vd
d VTNltVinltVdd/2 saturation linear Vdd
Vdd/2 saturation saturation Vdd/2
Vdd-VTPgtVingtVdd/2 linear saturation 0
Vdd linear cut-off 0
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The CMOS inverter
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The CMOS inverter

• Propagation delay
• Main origin load capacitance
• To reduce the delay
• Reduce CL
• Increase kn and kp. That is, increase W/L

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The CMOS inverter

• CMOS power budget
• Dynamic power consumption
• Charging and discharging of capacitors
• Short circuit currents
• Short circuit path between power rails during
  switching
• Leakage
• Leaking diodes and transistors

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The CMOS inverter

• The dynamic power dissipation is a function of
• Frequency
• Capacitive loading
• Voltage swing
• To reduce dynamic power dissipation
• Reduce CL
• Reduce f
• Reduce Vdd ? The most effective action

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The CMOS inverter
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The CMOS inverter
substrate contact (p)
n-well contact (n)
substrate contact (p)
n-well contact (n)
n-well
polysilicon
diffusion contacts
n-well
polysilicon
diffusion contacts
n diffusions
p diffusions
n diffusions
p diffusions
polysilicon contacts
polysilicon contacts
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Why The CMOS inverteris Better??

• 1) Low DC Power Consumption
• 2) Abrupt well defined Voltage transfer
  Characteristic
• 3) Noise Immunity due to Low impedance between
  logic levels and Supply/Gnd.
• Symmetry between Tfall Trise.
• High Density Si real estategtYieldgtCost!
• Highly IntegratedgtActive High input
  Impedancegt Composition equality.
• No real trade off between 1,2,3,4,5 6