Effects of Onchip Inductance on Power Distribution Grid

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Effects of On-chip Inductance on Power
Distribution Grid

• Atsushi Muramatsu Kyoto Univ.
• Masanori Hashimoto Osaka Univ.
• Hidetoshi Onodera Kyoto Univ.
• hasimoto_at_ist.osaka-u.ac.jp

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Inductance in power grid analysis

• Conventionally
• Inductance of package and bonding
• dominant
• considered
• Inductance of on-chip wire
• many elements yet small
• not considered
• Recently
• Increase in clock freq.
• higher freq. component of noise
• wL increases as freq. increases
• Reduction in L of package and bonding
• Relatively on-chip L increases

Advance in packages
QFP
FCBGA (Bump Array)
Q on-chip inductance important?
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Previous works

• Mezhiba, Kluwer 2004
• Outline of on-chip inductance aware analysis
• Noise propagates as a wave
• Y.-M. Lee, TCAD02
• Fast simulation based on transmission line theory
• W.H. Lee, ISQED04
• Discussion on wire structures
• C.W. Fok, Intl Journal of High Speed Elec.
  Sys 02
• Discussion on error due to ignoring on-chip
  inductance
• Effect of on-chip inductance becomes significant
  when package impedance is small.

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Contribution of this work

• Experimental studies
• To evaluate effect of on-chip inductance under
  various power consumption distribution
• To reveal that decap. position is important to
  mitigate on-chip inductance effect as well as to
  suppress power noise
• To study robustness of power grid with respect to
  grid pitch, wire area and PG spacing

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Power grid structure

• Power and ground wires are routed in pairs.
• Only topmost power/ground grid is considered.
• Bumps are uniformly attached at some of crossing
  points.

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Equivalent circuit model
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Experimental setup(single current source)

• A single current source excited
• All NAND2 gates in 3,000mm2 switch
• Tr 50, 66, 100ps (constant power dissipation)
• P/G wire 10mm wide, 1mm thick, 100mm pitch
• 130nm technology, supply voltage 1.2V
• 2x2mm2 chip, 99 bumps for P/G
• Each bump 0.5nH, 1W
• Full PEEC model all mutual inductances
  considered.
• Half area is occupied by NAND2 gates

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Difference between w/ and w/o on-chip inductance

• Big difference between w/ and w/o on-chip
  inductance
• Without on-chip inductance, not strong dependence
  on Tr.

With on-chip L, quadratic dependence on Tr
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Decap size, position and noise amplitude

• Decap 100mm far hardly works.
• Decap at current source works well.

Decap position is important for noise
suppression when on-chip inductance is
significant.
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Experimental setup(realistic power consumption)

• 0.13mm technology, 1.2V supply voltage
• Chip size 6x6mm2, 100100 bumps for P/G
• Each bump 0.5nH, 1W
• PG wires pitch 300mm, width 30mm, thickness 1mm
• Full PEEC model all mutual inductances
  considered
• Half area is occupied by NAND2 gates
• Power consumption models
• Uniform 20 of transistors switching uniformly
• Unbalance 50 of transistors switching at
  center, and 10 at periphery. Total power
  consumption is the same with uniform case
• Current transition time Tr 50ps

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Power consumption distribution and power noise
Uniform power dissipation
Unbalance power dissipation
on-chip L effect small
on-chip L effect significant
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Why on-chip L hardly affects voltage fluctuation
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Decap placement and power noise
Adaptive decap placement
Uniform decap placement
work well on-chip L effect small when decap is
enough
not work efficiently on-chip L effect large
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Comparison between PEEC and decoupled models
When paired PG wires are coupled perfectly,
self-inductance L-M, mutual-inductance
0 (decoupled model)
Difference exists, yet not significant. Decoupled
model is used for larger grid analysis.
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Grid pitch and power noise
Wire area is fixed to 20.
Noise voltage is reduced as grid pitch decreases.
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Wire area and power noise
10 reduction
7 reduction
Grid pitch 300mm
Grid pitch 50mm

• Wire area increase reduces noise, yet not
  drastically.
• Finer grid is more efficient than large wire area.

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Conclusion

• Evaluated effects of on-chip inductance
• Decap position is important
• Non-uniform power consumption distribution
  increases effects of on-chip L
• Adaptive decap insertion based on local power
  consumption mitigates on-chip L effects
• Grid pitch is more important than wire area for
  improving power grid robustness.