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EFFICIENT REALIZATION OF XOR-INTENSIVE FUNCTIONS
IN FPGAs
Department of ECE University of
Saskatchewan Seok-Bum Ko (seokbum.ko_at_usask.ca)
2
1. INTRODUCTION

• Emerging XOR Intensive Applications
• - error detecting/correcting
• - data encryption/decryption
• - arithmetic circuits
• by AND/OR-based EDA tools?

3
AND/OR EXPRESSION REALIZATION
xy
00
01
11
10
00
01
zw
11
10

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AND/XOR EXPRESSION REALIZATION
xy
00
01
11
10
00
01
zw
11
10
5
2. TECHNOLOGY MAPPING FOR AND/XOR EXPRESSIONS

• Shannons Davios Expansion
• Example
• Proposed Technology Mapping Method

6
SHANNONS EXPANSION

• An arbitrary logic function f(x1, x2,, xn) can
  be expanded as
• where

7
POSITIVE DAVIOS EXPANSION

• An arbitrary logic function f(x1, x2,, xn) can
  be expanded as
• where
• 
  

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NEGATIVE DAVIOS EXPANSION

• An arbitrary logic function f(x1, x2,, xn) can
  be expanded as
• where
• 
  and

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EXAMPLE OF SHANNON / DAVIO EXPANSION

• f x1x2x3x4x5 ? x1x3x4x5 ? x2x3x4x5 ? x1x3x4x5
• x3x4x5 ? x2x3x4x5
• x2x3x4x5 ? x2x3x4x5 ? x3x4x5
• x3x4x5 ? x2x3x4x5 ? x3x4x5
• fs x1(x3x4x5 ? x2x3x4x5) ?
• x1 (x2x3x4x5 ? x2x3x4x5 ? x3x4x5)
• fd (x3x4x5 ? x2x3x4x5) ?
• x1 (x3x4x5 ? x2x3x4x5 ? x3x4x5)
• f-d (x2x3x4x5 ? x2x3x4x5 ? x3x4x5) ?
• x1 (x3x4x5 ? x2x3x4x5 ? x3x4x5)

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PROPOSED TECHNOLOGY MAPPING METHOD

• if ( of input variables of f) ? 5
• exit f can be fit into a CLB perfectly
• else go to step 2
• Pick the LFU input variable in f and let it be xi
• Decompose f into
• if ( of input variables in ) gt 5
• replace f with new and go to step 2
• else go to step 5
• if ( of input variables in ) gt 5
• replace f with new and go to step 2
• else go to step 6
• Update f with the new and
• Exit

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PREPROCESSING FOR inc_p
3. EXAMPLE

• 1. inc.pla original format
• 2. inc.vhd VHDL format
• 3. inc_p_t.vhd parity prediction circuit
• 4. minimizer(p) Logic Optimization
• 5. inc_p.vhd optimized parity circuit
• 6. Technology Mapping (next slides)

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EXAMPLE (inc_p) OF TECHNOLOGY MAPPING

• Step 1 ( of input variables in inc_p) 7
• f -01-235 ? 2-35 ? 0-1-2-3-4-6 ? 012-35 ? 0-1-3
  ? -0135-6 ?
• -0235-6 ? -012-3-4-56 ? -02 ? -01-2-6 ?
  -1-2-3-4
• - not, input variable, -0
• Step 2 i 4
• Step 3
• -01-235 ? 2-35 ? 0-1-2-3-6 ? 012-35 ? 0-1-3 ?
  -0135-6 ?
• -0235-6 ? -012-3-56 ? -02 ? -01-2-6 ? -1-2-3
• -01-235 ? 2-35 ? 012-35 ? 0-1-3 ? -0135-6 ?
• -0235-6 ? -02 ? -01-2-6
• 0-1-2-3-6 ? -012-3-56 ? -1-2-3
• f
• (-01-235 ? 2-35 ? 0-1-2-3-6 ? 012-35 ? 0-1-3
  ? -0135-6 ?
• -0235-6 ? -012-3-56 ? -02 ? -01-2-6 ?
  -1-2-3)
• ? 4(0-1-2-3-6 ? -012-3-56 ? -1-2-3)

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6
13

• Step 4 Go to Step 2 since of input variables
  in is six let f
• Step 2 i 6
• Step 3
• -01-235 ? 2-35 ? 0-1-2-3 ? 012-35 ? 0-1-3 ?
  -0135 ?
• -0235 ? -02 ? -01-2 ? -1-2-3
• -01-235 ? 2-35 ? 012-35 ? 0-1-3 ? -012-3-5 ?
  -02 ? -1-2-3
• 0-1-2-3 ? -0135 ? -0235 ? -01-2? -012-3-5
• f
• (-01-235 ? 2-35 ? 0-1-2-3 ? 012-35 ? 0-1-3 ?
  -0135 ?
• -0235 ? -02 ? -01-2 ? -1-2-3)
• ? 6(0-1-2-3 ? -0135 ? -0235 ? -01-2 ?
  -012-3-5 )

5
5
14

• Step 4 Go to Step 5 since of input variables
  in is five
• Step 5 Go to Step 2 since of input variables
  in is six let f
• Step 2 i 5
• Step 3
• 0-1-2-3-6 ? -012-36 ? -1-2-3
• 0-1-2-3-6 ? -1-2-3
• -012-36
• f
• (0-1-2-3-6 ? -012-36 ? -1-2-3) ? 5(-012-36)

5
5
15

• Step 4 Go to Step 5 since of input variables
  in 5
• Step 5 Go to Step 6 since of input variables
  in 5
• Step 6
• f
• (-01-235 ? 2-35 ? 0-1-2-3 ? 012-35 ? 0-1-3 ?
  -0135 ? -0235
• ? -02 ? -01-2 ? -1-2-3)
• ? 6(0-1-2-3 ? -0135 ? -0235 ? -012-3-5 ?
  -01-2 ? -012-3-5)
• ? 4(0-1-2-3-6 ? -012-36 ? -1-2-3) ?
  5(-012-36)
• Step 7 Exit

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CLB STRUCTURE FOR inc_p
4-input LUT
N. C
CLB
i0,i1,i2,i3,i5
fa
5
i6
CLB
i0,i1,i2,i3,i5
3-input LUT
5
i4
f
4-input LUT
CLB
i0,i1,i2,i3,i6

5
i5
CLB
i0,i1,i2,i3,i6
5
N. C
CLB
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FPGA STRUCTURE OF inc_p
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4. RESULTS

• MCNC Benchmark Circuits
• Xilinxs XC4010 (400 CLBs)
• Xilinxs Foundation Software
• Microsoft Visual C 6.0

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DESIGN FLOW
MCNC Benchmark
Convert to VHDL
Parity Prediction Circuit (VHDL)
Convert to AND/XOR (VHDL)
Xilinx Foundation
Decomposition (Davio)
Xilinx Foundation
Decomposition (Shannon)
FPGA
FPGA
FPGA
FPGA
Direct Approach
AND/XOR Direct
Proposed Davio Approach
Shannon Approach
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NUMBER OF CLBs (PARITY PREDICTION CIRCUITS)
A of CLBs when optimized for speed in Xilinx
Foundation
B of CLBs when optimized for area in Xilinx
Foundation
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TOTAL EQUIVALENT GATE COUNTS (PARITY PREDICTION
CIRCUITS)
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MAX COMBINATIONAL PATH DELAY MAX NET DELAY
(PARITY PREDICTION CIRCUITS)
A Maximum Combinational Path Delay (ns)

B Maximum Net Delay (ns)
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NUMBER OF CLBs (MCNC BENCHMARK CIRCUITS)
A of CLBs when optimized for speed in Xilinx
Foundation 2.1i
B of CLBs when optimized for area in Xilinx
Foundation 2.1i
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5. CONCLUSIONS

• Investigated AND/OR and AND/XOR technology
  mapping methods in FPGA environment
• Proposed a Davios Expasnion-based technology
  mapping method
• Conducted experiments using MCNC benchmark
  circuits considering Direct Approach, AND/XOR
  Direct, and Proposed Davio Approach

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• Superior for XOR intensive functions
• - of CLBs reduced by 67.6a and 57.7b
• - Gate Counts reduced by 65.5
• - Max. Comb. Path Delay reduced by 56.7
• - Max. Net Delay reduced by 80.5
• Competitive for non XOR intensive functions
• - of CLBs 12.5 vs 13.5a/12.1b
• a speed optimized Direct Approach
  b area optimized Direct
  Approach

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CURRENT WORK
Area and Delay Results of MCNC Benchmarks Parity
Prediction Circuits
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CURRENT WORK cont.
Area-Delay Product Results of MCNC Benchmarks
Parity Prediction Circuits
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CURRENT WORK cont.
Area and Delay Results of MCNC Benchmark Circuits
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FUTURE WORK

• Error correcting / detecting circuits
• Data encryption / decryption
• Computer arithmetic circuits
• Floating Point Unit and its applications