EET 3350 Digital Systems Design Textbook: John Wakerly Chapter 7: 712

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EET 3350 Digital Systems Design Textbook John
Wakerly Chapter 7 7-12

• Sequential-Circuit Design Using VHDL

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Todays Agenda

• VHDL Sequential Statements
• process blocks
• conditional execution (branching)
• iteration (looping)
• Enumerated data types
• Example VHDL Designs of FSMs

Note Skip sections 7.11 ABEL and 7.13 Verilog
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Process Statement

• Main construct for Behavioral Modeling
• The process statement is a concurrent construct
  which performs a set of consecutive (sequential)
  actions once it is activated. Thus, only
  Sequential Statements are allowed within the
  process block.

Optional
Optional
Constant/Variables No Signal Declarations Allowed
process_label process (Sensitivity_List) --
process declarations begin --
sequential statements end Process
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VHDL Process Statement

• Unless the sequential part is suspended
• it executes in zero real and delta time
• it repeats itself forever

unless suspended
begin
-- sequential part
zero time
end process
repeats forever
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VHDL Process Statement

• Whenever a signal in the Sensitivity_List of the
  Process changes, the Process is activated.
• After executing the last statement, the Process
  is suspended until one (or more) Signal in the
  Process Sensitivity_List changes value where it
  will be reactivated.
• A Process Statement without a Sensitivity_List is
  always active, i.e., After the last statement is
  executed, execution returns to the first
  statement and continues (infinite looping).
• If no Sensitivity_List exists, a Process may be
  activated or suspended using the wait statement.
• Conditional and selective signal assignments are
  strictly concurrent and cannot be used in a
  process.

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VHDL Sequential Statements

• VHDL process statement syntax

LABEL1 process (sensitivity list ltoptionalgt)
-- declarations begin -- process
statements like -- wait on CLK, RESET --
wait until CLK'event and CLK'1' end process
a process is event driven
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VHDL Sequential Statements

• Syntax for the wait statement

wait on sig1, sig2, sigN -- wait for event on
one or more of signals wait until
ltconditiongt -- wait until condition is
true wait for timeperiod -- wait for time to
elapse
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VHDL Sequential Statements

• The wait statement can be placed anywhere in
  process block
• execution proceeds until wait is encountered
• execution then suspends until wait is satisfied
• A process block may have multiple wait statements
• Exception
• A process with a sensitivity list cannot contain
  any wait statements!

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VHDL Sequential Statements

• Conditional Process Execution
• Process execution is in order, top-to-bottom
  unless a conditional execution statement is
  encountered
• The types of VHDL conditional statements are
  similar to their corresponding programming
  language constructs
• case
• if then - else
• Some CAD tools may not implement all forms

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VHDL Sequential Statements

• Syntax for the case statement

case expression is when choice_1 gt
-- sequential statements when choice_2 gt
-- sequential statements . . .
when choice_n gt -- sequential
statements when others gt -- default
condition -- sequential statements end
case
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VHDL Sequential Statements

• Syntax for the ifthenelse statement

if ltconditiongt then -- sequential
statements elsif ltconditiongt then --
sequential statements else -- sequential
statements end if
If a ltconditiongt is true the associated
sequential statements are executed and the rest
of the group are skipped. No fall through! NOTE
the else if case is elsif (one word, e
missing)
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Simple Decade Counter Example
architecture behave of deccnt is signal cntval
std_logic_vector(3 downto 0) cntr process
(clk, reset) begin if (reset 1)
then cntval lt 0000 elsif (clkevent and
clk 1) then cntval lt cntval
0001 if (cntval 1001) then cntval
lt 0000 end if end if end process end
behave
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Enumerated Type Definition

• You can define your own enumerated data types
• useful when defining states and transitions
• basic syntax is
• type type_name is (value_list)
• Once declared, the new data type is used to
  define new signals of that type

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Enumerated Type Example

• Basic syntax

type state_type is (reset, sync, load,
out) signal pstate state_type ss process
(clk) begin if (clkevent and clk 1)
then case pstate is when reset gt when
sync gt etc end if end process
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VHDL Sequential Statements

• Process iteration
• Allows repetitive execution (looping)
• Three basic forms
• loop end loop (infinite)
• for ltvar in rangegt loop end loop
• while ltconditiongt loop end loop
• All looping statements may have an optional label
  as prefix

We wont use loops very often as they cannot be
synthesized.
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Loop Statements

• VHDL loop statement syntax and examples

• while condition loop
• -- sequential statements
• end loop
• for identifier in range loop
• -- sequential statements
• end loop

• while index gt 0 loop
• index index -1
• end loop
• for count in 0 to 127 loop
• count_out lt count
• wait for 5 ns
• end loop
• for i in 1 to 10 loop
• count count 1
• end loop

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VHDL Sequential Statements

• The next statement
• Used to terminate current pass through loop
• Four forms
• next (absolute)
• next when ltconditiongt
• next label
• next label when ltconditiongt
• The last two forms allow termination to the end
  of an outer loop

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VHDL Sequential Statements

• The exit statement
• Used to terminate entire loop execution
• Four forms
• exit (absolute)
• exit when ltconditiongt
• exit label
• exit label when ltconditiongt
• The last two forms allow termination from an
  inner loop to the end of an outer loop

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FSM Design Examples

• Moore Pattern Recognizer
• Mealy Pattern Recognizer
• BCD to Excess-3 Code Converter

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Moore FSM

• State diagram for a Moore FSM that recognizes the
  sequence 10

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Moore FSM in VHDL
type state is (S0, S1, S2) signal Moore_state
state U_Moore process(clock,
reset) begin if(reset 1) then Moore_state
lt S0 elsif (clock 1 and clockevent)
then case Moore_state is when S0 gt if
input 1 then Moore_state lt S1 end
if when S1 gt if input 0 then
Moore_state lt S2 end if when S2 gt if
input 0 then Moore_state lt S0 else
Moore_state lt S1 end if end case end
if end process output lt 1 when Moore_state
S2 else 0
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Mealy FSM

• State diagram for a Mealy FSM that recognizes the
  sequence 10

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Mealy FSM in VHDL
type state is (S0, S1) signal Mealy_state
state U_Mealy process(clock,
reset) begin if(reset 1) then Mealy_state
lt S0 elsif (clock 1 and clockevent)
then case Mealy_state is when S0 gt if
input 1 then Mealy_state lt S1 end
if when S1 gt if input 0 then
Mealy_state lt S0 end if end case end
if end process output lt 1 when (Mealy_state
S1 and input 0) else 0
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FSM Model

• Generalized block diagram for a FSM machine

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Sequential State Machines in VHDL

• The two basic techniques are
• The 3-process definition method
• next-state combinational logic process
• state register process
• output combinational logic process
• The 1-process and concurrent assignment method
• A single process defines state register and
  transitions
• Conditional or selected concurrent assignment
  define the output combinational logic
• Examples follow

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VHDL FSM

• 2-bit binary up counter
• A simple ring counter
• The output is the count (from state register,
  flip-flops)

Y PS
State Diagram
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VHDL FSM

• State Table

State Assignment
Let S0 reset state
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VHDL Code Header Information

• --------------------------------------------------
  --------------
• --
• -- Program fsm1.vhd
• --
• -- Description 2-bit binary up counter
• --
• -- Author Mary Peters
• -- Date
• -- Revisions
• --------------------------------------------------
  -------------
• -- Signal I/O
• --------------------------------------------------
  --------------
• -- Signal name Direction
  Description
• -- clock,reset in
  clock,reset
• -- count out
  output count
• --------------------------------------------------
  --------------

Develop your own header, but do use one for every
program you write
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VHDL Code Entity Declaration

• library ieee
• use ieee.std_logic_1164.all
• use ieee.std_logic_arith.all
• use ieee.std_logic_unsigned.all
• -- define entity
• entity fsm1 is
• port ( clk,reset in std_logic
• count out std_logic_vector(1 downto 0)
• )
• end entity fsm1

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VHDL Code Architecture

• -- define architecture
• architecture fsm of fsm1 is
• -- define constants
• constant s0 std_logic_vector(1 downto 0)
  "00"
• constant s1 std_logic_vector(1 downto 0)
  "01"
• constant s2 std_logic_vector(1 downto 0)
  "10"
• constant s3 std_logic_vector(1 downto 0)
  "11"
• signal ns,ps std_logic_vector(1 downto 0)
• begin

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VHDL Code State Logic

• --
• -- this process executes the FF control logic
• --
• process (ps)
• begin
• ns lt s0 --this is the default
  state/output
• case ps is
• when s0 gt ns lt s1
• when s1 gt ns lt s2
• when s2 gt ns lt s3
• when s3 gt ns lt s0
• when others gt ns lt s0 --default
  condition
• end case
• end process

State Diagram for F Logic
Note we only need to describe the behavior,
VHDL will figure out the functional
relationships
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VHDL Code Register Logic

• --
• -- This process includes the registers
  implicitly
• --
• reg process (clk, reset, ns)
• begin
• if(reset '0') then
• ps lt s0
• elsif (clk'event and clk '1') then
• ps lt ns
• end if
• end process reg

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VHDL Code Output H Logic

• --
• -- Use concurrent statement to implement output
  Logic
• --
• count lt ps
• end architecture fsm

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Gate Level Logic Diagram
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Designing with VHDL

• Design a code converter that converts an 8-4-2-1
  binary-coded decimal (BCD) digit to an
  excess-3-coded decimal digit.
• The input (X) and output (Z) are to be serial
  with the least significant digit bit first.
• After receiving four input bits, the circuit
  should reset to its initial state, ready to
  receive another BCD digit.

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Designing with VHDL

• The code conversion is accomplished according to
  the table below

The excess-3 code is formed by adding 00112 (310)
to the BCD digit.
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Designing with VHDL

• The code conversion is accomplished by adding
  0011

t3 t2 t1 t0 X3 X2 X1 X0 0 .0 1 .1 Z3 Z2
Z1 Z0
We can look at the four clock times and analyze
what happens with respect to the input bit (Xi)
and the output bit (Zi).
Xi / Zi
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Designing with VHDL

• State diagram for the BCD to Excess-3 code
  converter

Reset
S0
t0
add X0 1
X/Z
1/0
0/1
S1
S2
No Carry
Carry
t1
add X1 1
We add 3 (0011) to the incoming BCD digit. Thus,
at time t0 we will either get Z 01 1 with no
carry or Z 11 0 with a carry.
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Designing with VHDL

• State diagram for the BCD to Excess-3 code
  converter

Reset
S0
t0
add X0 1
X/Z
1/0
0/1
S1
S2
Carry
No Carry
t1
add X1 1
1/0
0/1
0/0,1/1
S3
S4
Carry
No Carry
t2
add X2 0
At time t1 in state S1 we will either get Z
001 1 with no carry or Z 011 0 with a
carry. In state S2 (where we previously had a
carry) we get Z 101 0 (carry) or Z 111
1 (carry)
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Designing with VHDL

• State diagram for the BCD to Excess-3 code
  converter

Reset
S0
t0
add X0 1
X/Z
1/0
0/1
S1
S2
Carry
No Carry
t1
add X1 1
1/0
0/1
0/0,1/1
S3
S4
Carry
No Carry
t2
add X2 0
0/1
0/0,1/1
1/0
S5
S6
Carry
No Carry
t3
add X2 0
Z0000 (no carry) Z0101 (no carry)
Z1001 (no carry) Z1100 (carry)
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Designing with VHDL

• State diagram for the BCD to Excess-3 code
  converter

Reset
S0
t0
add X0 1
X/Z
1/0
0/1
S1
S2
Carry
t1
add X1 1
1/0
0/1
0/0,1/1
0/1
0/0,1/1
S3
S4
Carry
t2
add X2 0
0/1
0/0,1/1
1/0
S5
S6
Carry
t3
add X2 0
Z0000 (reset) Z0101 (reset)
Z1001 (reset) Z1100 (not possible)
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Designing with VHDL

• State diagram for the BCD to Excess-3 code
  converter

State Table
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Designing with VHDL

• Size of memory (without attempting reduction)

Seven states means that we need three Flip-Flops.
Each state will have a 3-bit binary label.
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Designing with VHDL

• State assignment minimize changes in Q

maximize adjacent state assignments
ideal world S0 ? S1,S2,S5,S6 S1 ? S0,S3,S4 S2 ?
S0,S4 S3 ? S1,S5 S4 ? S1,S2,S5,S6 S5 ? S0,S3 S6 ?
S0,S4
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Designing with VHDL

• State assignment, 3-bit binary label

We cannot achieve all adjacencies, for 3
variables there is a maximum of 3 adjacencies each
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Designing with VHDL

• State assignment, 3-bit binary label

We cannot achieve all adjacencies, for 3
variables there is a maximum of 3 adjacencies each
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The Old-Fashioned Way

• Karnaugh Maps

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The Old-Fashioned Way

• Circuit resulting from the simplified equations

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Designing with VHDL

• The VHDL code for this circuit begins with the
  usual entity block

entity codeConvert is port (X, CLK in bit
Z out bit) end codeConvert
entity matches the block diagram
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Designing with VHDL

• The code for a behavioral architecture is

architecture Table of codeConvert is signal
State, Nextstate integer 0 begin process
(State,X) --Combinational Network for
output begin case State is when 0 gt if
x0 then zlt1 Nextstatelt1 end if if
x1 then zlt0 Nextstatelt2 end if when
1 gt if x0 then zlt1 Nextstatelt3 end
if if x1 then zlt0 Nextstatelt4 end
if when 2 gt if x0 then zlt0
Nextstatelt4 end if if x1 then zlt1
Nextstatelt4 end if when 3 gt if x0
then zlt0 Nextstatelt5 end if if x1
then zlt1 Nextstatelt5 end if when 4
gt if x0 then zlt1 Nextstatelt5 end
if if x1 then zlt0 Nextstatelt6 end
if when 5 gt if x0 then zlt0
Nextstatelt0 end if if x1 then zlt1
Nextstatelt0 end if when 6 gt if x0
then zlt1 Nextstatelt0 end if when others
gt null --should not occur end case end
process
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Designing with VHDL

• The code for a behavioral architecture is

process (CLK) --State Register begin if
(CLKevent and CLK1) then --Rising edge of
clock State lt Nextstate end if end
process end Table
This second process causes the state transition
to occur in synchronization with the clock
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Assignment

• Read textbook sections 8.1 and 8.2
• Redo the BCD to Excess-3 converter using a binary
  counting-order state assignment.