EE5342 - PowerPoint PPT Presentation

1 / 40
About This Presentation
Title:

EE5342

Description:

for Flat-Band. Surface effect analogous to the extr Debye ... Flat-band parameters. for p-channel (n-subst) L25 April 20. 28. Inversion for p-Si. Vgate VTh VFB ... – PowerPoint PPT presentation

Number of Views:25
Avg rating:3.0/5.0
Slides: 41
Provided by: drronald7
Learn more at: https://www.uta.edu
Category:
Tags: ee5342 | flat

less

Transcript and Presenter's Notes

Title: EE5342


1
EE5342 Semiconductor Device Modeling and
CharacterizationLecture 25 - Spring 2004
  • Professor Ronald L. Carter
  • ronc_at_uta.edu
  • http//www.uta.edu/ronc/

2
Ideal 2-terminalMOS capacitor/diode
Vgate
conducting gate, area LW
-xox
SiO2
0
y
0
L
silicon substrate
tsub
Vsub
x
3
Band models (approx. scale)
metal
silicon dioxide
p-type s/c
Eo
Eo
qcox 0.95 eV
Eo
qcSi 4.05eV
qfm 4.1 eV for Al
Ec
qfs,p
Eg,ox 8 eV
Ec
EFm
EFi
EFp
Ev
Ev
4
Flat band condition (approx. scale)
Al
SiO2
p-Si
q(fm-cox) 3.15 eV
q(cox-cSi)3.1eV
Ec,Ox
qffp 3.95eV
EFm
Ec
Eg,ox8eV
EFi
EFp
Ev
Ev
5
Equivalent circuitfor Flat-Band
  • Surface effect analogous to the extr Debye length
    LD,extr eVt/(qNa)1/2
  • Debye cap, CD,extr eSi/LD,extr
  • Oxide cap, COx eOx/xOx
  • Net C is the series comb

COx
CD,extr
6
Accumulation for Vgatelt VFB
Vgatelt VFB
-xox
SiO2
EOx,xlt0
0
holes
p-type Si
tsub
Vsub 0
x
7
Accumulationp-Si, Vgs lt VFB
Fig 10.4a
8
Equivalent circuitfor accumulation
  • Accum depth analogous to the accum Debye length
    LD,acc eVt/(qps)1/2
  • Accum cap, Cacc eSi/LD,acc
  • Oxide cap, COx eOx/xOx
  • Net C is the series comb

COx
Cacc
9
Depletion for p-Si, Vgategt VFB
Vgategt VFB
-xox
SiO2
EOx,xgt 0
0
Depl Reg
Acceptors
p-type Si
tsub
Vsub 0
x
10
Depletion forp-Si, Vgategt VFB
Fig 10.4b
11
Equivalent circuitfor depletion
  • Depl depth given by the usual formula xdepl
    2eSi(Vbb)/(qNa)1/2
  • Depl cap, Cdepl eSi/xdepl
  • Oxide cap, COx eOx/xOx
  • Net C is the series comb

COx
Cdepl
12
Inversion for p-SiVgategtVThgtVFB
Vgategt VFB
EOx,xgt 0
e- e- e- e- e-
Acceptors
Depl Reg
Vsub 0
13
Inversion for p-SiVgategtVThgtVFB
Fig 10.5

14
Approximation conceptOnset of Strong Inv
  • OSI Onset of Strong Inversion occurs when ns
    Na ppo and VG VTh
  • Assume ns 0 for VG lt VTh
  • Assume xdepl xd,max for VG VTh and it doesnt
    increase for VG gt VTh
  • Cd,min eSi/xd,max for VG gt VTh
  • Assume ns gt 0 for VG gt VTh

15
MOS Bands at OSIp-substr n-channel
Fig 10.9
16
Equivalent circuitabove OSI
  • Depl depth given by the maximum depl xd,max
    2eSi2fp/(qNa)1/2
  • Depl cap, Cd,min eSi/xd,max
  • Oxide cap, COx eOx/xOx
  • Net C is the series comb

COx
Cd,min
17
MOS surface statesp- substr n-channel
18
n-substr accumulation (p-channel)
Fig 10.7a
19
n-substrate depletion(p-channel)
Fig 10.7b
20
n-substrate inversion(p-channel)
Fig 10.7
21
Values for gate workfunction, fm
22
Values for fmswith metal gate
23
Values for fmswith silicon gate
24
Typical fms values
25
Flat band with oxidecharge (approx. scale)
Al
SiO2
p-Si
lt--Vox--gt-
q(Vox)
Ec,Ox
q(ffp-cox)
Ex
q(fm-cox)
Eg,ox8eV
Ec
EFm
EFi
EFp
q(VFB)
Ev
VFB VG-VB, when Si bands are flat
Ev
26
Flat-band parametersfor n-channel (p-subst)
27
Flat-band parametersfor p-channel (n-subst)
28
Inversion for p-SiVgategtVThgtVFB
Vgategt VFB
EOx,xgt 0
e- e- e- e- e-
Acceptors
Depl Reg
Vsub 0
29
Approximation conceptOnset of Strong Inv
  • OSI Onset of Strong Inversion occurs when ns
    Na ppo and VG VTh
  • Assume ns 0 for VG lt VTh
  • Assume xdepl xd,max for VG VTh and it doesnt
    increase for VG gt VTh
  • Cd,min eSi/xd,max for VG gt VTh
  • Assume ns gt 0 for VG gt VTh

30
MOS Bands at OSIp-substr n-channel
31
Computing the D.R. W and Q at O.S.I.
Ex
Emax
x
32
Calculation of thethreshold cond, VT
33
Equations forVT calculation
34
Fully biased n-MOScapacitor
VG
Channel if VG gt VT
VS
VD
EOx,xgt 0
e- e- e- e- e- e-
n
n
p-substrate
VsubVB
Acceptors
Depl Reg
y
0
L
35
MOS energy bands atSi surface for n-channel
Fig 8.10
36
Computing the D.R. W and Q at O.S.I.
37
Qd,max and xd,max forbiased MOS capacitor
Fig 8.11
xd,max (mm)
38
Fully biased n-channel VT calc
39
n-channel VT forVC VB 0
Fig 10.20
40
References
Semiconductor Physics Devices, by Donald A.
Neamen, Irwin, Chicago, 1997. Device
Electronics for Integrated Circuits, 2nd ed., by
Richard S. Muller and Theodore I. Kamins, John
Wiley and Sons, New York, 1986
Write a Comment
User Comments (0)
About PowerShow.com