High Level Language (HLL) Design Methodology Handel C

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High Level Language (HLL)Design
MethodologyHandel C
ECE 448 Lecture 12
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Main sources

• Celoxica Ltd.
• Handel-C Language Reference Manual
• available on WebCT

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Behavioral Synthesis
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Behavioral Synthesis
I/O Behavior
Target Library
Algorithm
Behavioral Synthesis
RTL Design
Logic Synthesis
Classic RTL Design Flow
Gate level Netlist
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Need for High-Level Design

• Higher level of abstraction
• Modeling complex designs
• Reduce design efforts
• Fast turnaround time
• Technology independence
• Ease of HW/SW partitioning

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Advantages of Behavioral Synthesis

• Easy to model higher level of complexities
• Smaller in size source compared to RTL code
• Generates RTL much faster than manual method
• Multi-cycle functionality
• Loops
• Memory Access

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High-Level Languages

• C/C-Based
• Handel C Celoxica Ltd., UK
• Impulse C Impulse Accelerated Technologies
• Catapult C Impulse Accelerated Technologies
• System C The Open SystemC Initiative
• Java-based
• Forge Xilinx
• JHDL Brigham Young University

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Other High-Level Design Flows

• Matlab-based
• System Generator for DSP Xilinx
• AccelChip DSP Synthesis AccelChip
• GUI Data-Flow based
• Corefire Annapolis Microsystems
• RC Toolbox DSPlogic

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Handel C Design Flow
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Design Flow
Executable Specification
Handel-C
VHDL
Synthesis
EDIF
EDIF
Place Route
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Handel-C/ANSI-C Comparisons
ANSI-C
HANDEL-C
Handel-C Standard Library
ANSI-C Standard Library
Preprocessors i.e. define
Parallelism
Pointers
Structures
Channels
Side Effects i.e. X Y
ANSI-C Constructs for, while, if, switch
Arbitrary width variables
Arrays
Bitwise logical operators
Enhanced bit manipulation
Recursion
Logical operators
Arithmetic operators
RAM, ROM
Signals
Functions
Floating Point
Interfaces
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Variables

• Only one fundamental type for variables int
• int 5 x
• unsigned int 13 y
• Default types
• char 8 bits
• short 16 bits
• long 32 bits

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Type Summary
Type Width
char 8 bits
unsigned char 8 bits
short 16 bits
unsigned short 16 bits
long 32 bits
unsigned long 32 bits
int Compiler
unsigned int Compiler
int n n bits
unsigned int n n bits
unsigned n n bits
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Arrays

• Same way as in ANSI-C
• int 6 x7
• 7 registers of 6 bits wide
• unsigned int 6 x 4 5 6
• 120 registers of 6 bits wide
• Index must be a compile time constant. If random
  access is required, consider using RAM or ROM

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Internal RAMs and ROMs

• Using ram and rom keywords
• ram int 6 a 43
• a RAM consisting of 43 entries of 6 bits wide
• rom int 16 b 4
• a ROM consisting of 4 entries of 16 bits wide
• RAMs and ROMs are accessed the same way that
  arrays are accessed in ANSI-C
• Index need not be a compile time constant

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Restrictions on RAMs and ROMs

• RAMs and ROMs are restricted to performing
  operations sequentially. Only one element may be
  addressed in any given clock cycle
• ram unsigned int 8 x 4
• x 1 x 3 1 illegal
• if (x 0 0)
• x 1 1 illegal

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Multi-port RAMs

• static mpram Fred
• ram ltunsigned 8gt ReadWrite256 (read/write
  port)
• rom ltunsigned 8gt Read256
• (read only port)
• Now we can read and write in a given
• clock cycle

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Dual Port Memory
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Handel-C Language (1)

• A subset of ANSI-C
• Sequential software style with a par construct
  to implement parallelism
• A channel chan statement allows for
  communication and synchronization between
  parallel branches
• Level of design abstraction is above RTL but
  below behavioral

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Handel-C Language (2)

• Each assignment and delay statement take one
  clock cycle
• Automatic generation of the state machine from an
  algorithmic description of the circuit in terms
  of parallel and sequential blocks
• Automatic scheduling of parallel and sequential
  blocks, that is the code following a group is
  scheduled only after that whole group has
  completed

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Parallelism
Statement
Parallel blocks
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Channel Communication
Statement
Channel
a
b
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Par construct - Examples
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Par constructs - timing
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Par construct shift register
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Channels
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Channel Communication

• Reading from a channel
• Channel ? Variable
• Writing to a channel
• Channel ! Expression
• No simultaneous write to or read from a single
  channel
• par par
• out ! 3 in ? x
• out ! 4 in ? y

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Scope and Variable Sharing

• int w
• void main(void)
• int x
• int y
• ..
• int z
• ..

y
w
x
z
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Statements
Statement Expansion
Variable Variable Variable 1
Variable -- Variable Variable 1
Variable Variable Variable 1
-- Variable Variable Variable 1
Variable Expression Variable Variable Expression
Variable - Expression Variable Variable Expression
Variable Expression Variable Variable Expression
Variable ltlt Constant Variable Variable ltlt Constant
Variable gtgt Constant Variable Variable gtgt Constant
Variable Expression Variable Variable Expression
Variable Expression Variable Variable Expression
Variable Expression Variable Variable Expression
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Bit Manipulation Operators
Operator Meaning
ltlt Shift left
gtgt Shift right
lt- Take least significant bits
\\ Drop least significant bits
_at_ Concatenate bits
Bit selection
Width (Expression) Width of expression
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Handel-C Example
void polyphase() ram int IN_WIDTH pin0_02,
pin0_12, pin0_22, pin0_32 ram int
IN_WIDTH pin1_02, pin1_12, pin1_22,
pin1_32 ram int IN_WIDTH pin2_02,
pin2_12, pin2_22, pin2_32 .. while (1)
par padd0_0half (pmult0_0half15 _at_
(pmult0_0half \\ 7)) (pmult0_1half15 _at_
(pmult0_1half \\ 7)) padd0_1half
(pmult0_2half15 _at_ (pmult0_2half \\ 7))
(pmult0_3half15 _at_ (pmult0_3half \\ 7))
pmult0_0half 0 pmult0_1half -7
(pin0_1half7 _at_ pin0_1half7 _at_
pin0_1half7 _at_ pin0_1half7 _at_
pin0_1half7 _at_ pin0_1half7 _at_
pin0_1half7 _at_ pin0_1half7 _at_
pin0_1half) pmult0_2half 109
(pin0_2half7 _at_ pin0_2half7 _at_
pin0_2half7 _at_ pin0_2half7 _at_ if (half)
par output0 ! (((padd0_019 _at_
padd0_01) (padd0_119 _at_ padd0_11)) \\
3)
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Take/drop operators
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Concatenation
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Bit selection
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Bit selection
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Width operator
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Arithmetic Operators
Operator Meaning
Addition
- Subtraction
Multiplication
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Relational Operators
Operator Meaning
Equal
! Not equal
lt Less than
gt Greater than
lt Less than or equal
gt Greater than or equal
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Relational Logical Operators
Operator Meaning
Logical AND
Logical OR
! Logical NOT
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Bitwise Logical Operators
Operator Meaning
Bitwise AND
Bitwise OR
Bitwise XOR
Bitwise NOT
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Compile Time Constant Expressions
Operator Meaning
/ Division
Modulo arithmetic
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Width of results (1)
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Width of results (2)
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Example - Accumulator

• void main(void)
• unsigned int 16 sum
• unsigned int 8 data
• chanin input
• chanout output
• sum 0
• do
• input ? data
• sum sum (0 _at_ data)
• while (data!0)
• output ! sum

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Handel C vs. C - functions

• Functions may not be called recursively, since
  all logic must be
• expanded at compile-time to generate hardware
• You can only call functions in expression
  statements.
• These statements must not contain any other calls
  or assignments.
• Variable length parameter lists are not
  supported.
• Old-style ANSI-C function declarations
• (where the type of the parameters is not
  specified) are not supported.
• main() functions take no arguments and return no
  values.
• Each main() function is associated with a clock.
• If you have more than one main() function in the
  same source file,
• they must all use the same clock.

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Handel-C Overview

• High-level language based on ISO/ANSI-C for the
  implementation of algorithms in hardware
• Allows software engineers to design hardware
  without retraining
• Clean extensions for hardware design including
  flexible data widths, parallelism and
  communications
• Based on Communicating Sequential Process model
• Independent parallel processes
• par construct to specify parallel computation
  blocks within a process
• Well defined timing model
• Each statement takes a single clock cycle
• Includes extended operators for bit manipulation,
  and high-level mathematical macros (including
  floating point)

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Handel C Additional Features
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Prialt statement
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Restrictions on using Prialt statement
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Macros and Functions
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Call by reference or value
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Call by reference or value
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Handel-C in VHDL (1)

• component handelc_component
• port (
• clk in std_logic
• sent_value in unsigned (3 downto 0)
• return_val out unsigned (3 downto 0)
• )
• end component

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Handel-C in VHDL (2)

• unsigned 4 x
• interface port_in (unsigned 1 clk with
  clockport1) ClockPort ()
• interface port_in (unsigned 4 sent_value)
  InPort ()
• interface port_out () OutPort (unsigned 4
  return_value x)
• set clock internal ClockPort.clk
• void main(void)
• unsigned 4 y
• y InPort.sent_value // Read from
  top-level VHDL
• x y // Write to
  top-level VHDL

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VHDL in Handel-C (1)

• ENTITY parmult IS
• port (
• clk IN std_logic
• a IN std_logic_VECTOR(7 downto 0)
• b IN std_logic_VECTOR(7 downto 0)
• q OUT std_logic_VECTOR(15 downto 0))
• END parmult
• interface parmult (unsigned 16 q)
  parmult_instance (unsigned 1 clk, unsigned 8 a,
  unsigned 2 b) with busformat "B(I)"

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VHDL in Handel-C (2)

• unsigned 8 x1, x2
• unsigned resultX
• interface parmult
• (unsigned 16 q)
• parmult_instance1
• (unsigned 1 clk __clock,
• unsigned 8 a x1,
• unsigned 8 b x2 )
• with busformat "B(I)"

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VHDL in Handel-C (3)

• while (1)
• par
• x1 some_value
• x2 some_value
• resultX parmult_instance1.q