Implementation of 802'11 Medium Access Controller

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Implementation of 802.11Medium Access Controller

• -Presented by
• Nirav Salot
• (02329008)
• -Guided by
• Prof. Kavi Arya

2
Introduction WLAN Card

• Block diagram - Wireless LAN Adapter

Antenna

802.11 MAC
Baseband Controller
RF Transceiver
Physical Air Interface
Interface to Application
Program Memory
3
Problem Motivation

• Many commercial product exist which implement
  IEEE 802.11 MAC.
• No implementation is available publicly.
• Changes suggested by researchers can not be
  implemented.
• To design implement the IEEE 802.11 MAC and
  make it available publicly.
• To fuel the development of dual MAC at IIT
  Bombay.
• The implementation will serve as a case study for
  such implementations.

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IEEE 802.11 MAC Block Diagram
802.11 MAC
Embedded MicroController
Host Interface Unit
Transceiver Attachment Interface Unit
Host Bus Signal
Physical Layer Interface Signal
Device Driver
Baseband Processor
Bus Controller Unit
Memory Interface Signal
Flash ROM, SRAM
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Device Driver

• It configures various 802.11 parameters.
• Provides simple interface such as send and
  receive for the transmission and reception of
  the frame.
• Implementation is independent of the protocol
  engine and more dependent on the OS, hardware
  architecture.

Host Bus Interface Unit

• Protocol bridge which provides plug and play
  interface for the WLAN adapter.
• Allows the IEEE 802.11 MAC and host to perform
  data transaction between each other.
• It is independent of the IEEE 802.11 MAC.

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External Memory

• External memory provides higher flexibility in
  protocol implementation at the cost of higher
  fetch/access time.
• Flash ROM contains program of 802.11 protocol,
  which is executed by the microcontroller.
• SRAM contains network data and temporary
  variables.

Embedded Microcontroller

• Implements all the functionality of 802.11 MAC as
  software.
• Executes the protocol engine stored in the
  external Flash ROM.
• Interacts with all the components as a set of
  command/status registers.
• Other components interact with it through the
  interrupt system.

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Transceiver Attachment Interface Unit

• Implements the time critical functionality of the
  protocol.
• Set of FSM implemented in hardware.
• Interfaces the Baseband controller to receive and
  transmit the frame.
• Contains various configuration, command and
  status register banks.
• Implements transmit and receive FIFOs to
  temporarily store the network data.
• Provides channel access indication.

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IEEE 802.11 MAC Architecture
Local Bus
Flash RAM
Embedded Microcontroller
Bus Request
TAI Unit
Rx Clock
Timer Counter
Clock Gen
Bus Arbiter Bridge
Tx Clock
Rx Data
Control Logic, Registers Banks FIFOs
CRC Gen
Tx Data
Bus Request
Interrupt Request
I2C Bus
I2C Controller
Interrupt Request
SRAM
Configuration, Command, Status Register Bank
Address
Bus Request
Control Logic
Control
Data
CS
CCA Logic
Bus Request
DMAC
Memory Bank
Host Bus Interface Bridge
Host Bus
Bus Request
IP Interconnect Bus
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IEEE 802.11 MAC Implementation Issues

• The Verilog/VHDL code of Host Interface Unit and
  Bus Control Unit is available as open source.
• Hardware / Software partitioning of the IEEE
  802.11 MAC protocol engine.
• Selection of the microcontroller on the basis of
  speed and architecture.
• External memory size and access time.
• Design and HDL implementation of the TAI unit.
• Implementation of remaining functionalities as a
  software.
• Integration of all the components to form IEEE
  802.11 Adapter.

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IEEE 802.11 Protocol

• Functionalities
• Authentication Deauthentication
• Privacy - WEP
• Medium Access
• Fragmentation and Defragmentation
• MSDU Delivery
• Time Synchronization
• Power Management
• Our Focus Distributed Coordination Function
  (DCF)
• Medium Access
• Fragmentation and Defragmentation
• MSDU Delivery

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DCF Set of Processes

• Validate_Mpdu Receives frame from BB processor,
  validates CRC checksum and frame length.
• Filter_Mpdu Receives frame from Validate_Mpdu,
  validates MAC address and duplicate frame.
• Rx_Coordination Receives frame from
  Filter_Mpdu, generates its response frame.
• Data_Pump Receives response frame from
  Rx_Coordination, pumps its data along with
  checksum to the BB processor.
• Channel_State Senses the channel and maintains
  the current state of it physically and virtually.
• Backoff Performs random backoff process.
• Defragment Receives frame from Rx_Coordination,
  performs its defragmentation.
• Tx_Coordination Receives frame from device
  driver, performs fragmentation, sets header
  fields etc for its transmission.

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DCF Processes Hardware Software Partition
Channel_State
Tx_Coordination
Validate_Mpdu
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TAI Unit Architecture
Data_Pump
Backoff
Channel_State
Bus Arbiter
Rx_Coordination
Memory
Filter_Mpdu
Validate_Mpdu
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(No Transcript)
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TAI Unit - Memory Map

• Total size 16 Kbytes.
• Control memory allocation map chunk size 16
  bytes.
• Data memory allocation map chunk size 255
  bytes.
• New packet start address no. of ones in the Old
  allocation map chunk size Frame start
  address.
• If Old allocation map is 0x001f and allocation
  for 4 chunk is required then new allocation map
  is 0x01ff.
• Separate memory for response frames such as ACK
  and CTS.
• Also act as a cache for main memory.

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Validate_Mpdu

• Reads INIT_CRC, GOOD_CRC etc from memory during
  Initialization phase.
• Buffers the data while acquiring bus control.
• Performs frame validation for CRC checksum,
  length and protocol version.
• Allocates the memory for frame and updates the
  allocation map.
• Passes the token to Filter_Mpdu.

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Filter_Mpdu

• Reads INIT_CRC from memory during Initialization
  phase.
• Reads the Frame Control Fields of the frame.
• Validates the frame for its MAC address and
  retransmission.
• Updates the allocation map and frees the memory
  if validation fails.
• Passes token to Rx_Coordination.

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Rx_Coordination

• Prepares the response frame such as ACK or CTS.
• Stores the response frame in the memory.
• Updates the control registers to indicate the
  pending reception and/or transmission.
• Frees the memory and updates the allocation map.
• Passes the token to Validate_Mpdu.

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Data_Pump

• Pumps the frame data into the Baseband processor.
• Generates CRC checksum for frame to be
  transmitted.
• Updates the allocation map to free the memory.
• Updates the control registers to indicate no
  pending transmission.

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Channel_State

• Senses the channel physically and virtually.
• CS Carrier Sense
• NAV Network Allocation Vector
• Maintains the current state of the channel and
  generates Idle, Busy and Slot signals.

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Backoff

• Performs exponential Backoff process.
• LFSR 16 Bit random no. generator.
• CntrlReg Start/Stop Backoff.
• ContWindowReg Current contention window.
• CountReg Current count.
• SlotCntReg Slot count no.

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Control Unit

• Central timing unit, controls the overall
  functioning of the TAI.
• Generates Reset and Enable.
• DevCntrlReg Ini, RxP and TxP.
• DevStatusReg Ready status of other blocks.
• Transmission TxFrameAddReg, TxFrameLenReg and
  TxP.
• Reception RxFrameAddReg, RxFrameLenReg, RxP and
  RxFrameStatusReg.
• Generates microcontroller interrupt uCInt0.
• SysTimeReg Current system time.
• LastFrameRxTimeReg Time of the last frame
  received.
• TxTimeDealyReg Delay in usec. for tranmission
  of the next frame.

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TAI Baseband Interface
Baseband Processor
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TAI Unit - Frame Reception
Control Unit
Bus Arbiter
Rx_Coordination
Filter_Mpdu
Memory
Baseband Processor
Validate_Mpdu
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TAI Unit - Frame Reception
Control Unit
Bus Arbiter
Rx_Coordination
MEMORY ALLOC_MAP
Filter_Mpdu
Memory
Validate_Mpdu
Baseband Processor
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TAI Unit - Frame Reception
Control Unit
Bus Arbiter
LAST_FRAME_RX_TIME
Rx_Coordination
MEMORY ALLOC_MAP
Filter_Mpdu
Validate_Mpdu
Baseband Processor
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TAI Unit - Frame Reception
Control Unit
Bus Arbiter
Rx_Coordination
MEMORY ALLOC_MAP
Filter_Mpdu
FRAME Data
Baseband Processor
Validate_Mpdu
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TAI Unit - Frame Reception
Control Unit
Bus Arbiter
Rx_Coordination
MEMORY ALLOC_MAP
Filter_Mpdu
FRAME Data
Baseband Processor
Validate_Mpdu
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TAI Unit - Frame Reception
Control Unit
Bus Arbiter
Rx_Coordination
MEMORY ALLOC_MAP
Filter_Mpdu
Frame Control Fields
FRAME Data
Baseband Processor
Validate_Mpdu
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TAI Unit - Frame Reception
Control Unit
Bus Arbiter
Rx_Coordination
MEMORY ALLOC_MAP
Filter_Mpdu
Frame Control Fields
FRAME Data
Baseband Processor
Validate_Mpdu
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TAI Unit - Frame Reception
Control Unit
DEV_CNTRL_REG
RX_FRAME_ADD
Bus Arbiter
RX_FRAME_LEN
RX_FRAME_STATUS
TX_FRAME_ADD
TX_FRAME_LEN
Rx_Coordination
MEMORY ALLOC_MAP
Filter_Mpdu
FRAME Data
Baseband Processor
Validate_Mpdu
ACK/CTS Frame
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TAI Unit Frame Transmission
Bus Arbiter
Baseband Processor
Data_Pump
uC
Control Unit
Memory
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TAI Unit Frame Transmission
Bus Arbiter
Baseband Processor
Data_Pump
uC
MEMORY ALLOC_MAP
Control Unit
DEV_CNTRL_REG
TX_FRAME_ADD
TX_FRAME_LEN
TX_TIME_DELAY
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TAI Unit Frame Transmission
Bus Arbiter
Baseband Processor
Data_Pump
uC
MEMORY ALLOC_MAP
Control Unit
DEV_CNTRL_REG
TX_FRAME_ADD
TX_FRAME_LEN
TX_TIME_DELAY
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TAI Unit Frame Transmission
Bus Arbiter
Baseband Processor
Data_Pump
uC
MEMORY ALLOC_MAP
Control Unit
DEV_CNTRL_REG
TX_FRAME_ADD
TX_FRAME_LEN
TX_TIME_DELAY
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HDL Implementation of TAI

• Hardware Description Languages VHDL, Verilog
  and Handel C
• Handel C implementation is faster.
• VHDL and Verilog have better hardware description
  capability and debugging information.
• Handel C implementation generates 2-3 times
  hardware as that of VHDL/Verilog.
• Our choice Verilog.

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Test Setup

• Behavioral description of Microcontroller and
  Baseband processor.
• No need for separate test bench.
• Channel Error model introduces random error in
  the frame.
• Simulates the practical scenario.

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Test Cases

• DCF Functionality
• Initialization Phase
• Reception of the frame
• Transmission of the frame
• Validation Functionality
• CRC error detection
• Frame length error detection
• MAC Address error detection
• Duplicate frame error detection

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Results

• Initialization phase 28-30 clock cycles.
• Microcontroller Backoff communication overhead
  7-8 clock cycles.
• Processing of incoming frame and generating
  response frame 122 clock cycles.
• Clock speed 100 MHz.
• Memory 16 Kbytes, Access time smaller than 10
  nsec.
• Buffer size at Validate_Mpdu 6-8 bytes.
• Data transfer rate of Baseband processor Depend
  upon the frame rate.

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Summary Future Work

• TAI unit is designed and implemented in Verilog.
• Most of the sub-units of the TAI unit is
  synthesized.
• FPGA implementation of the TAI unit should be
  done for further hardware testing.
• Remaining functionality is to be implemented as a
  set of program for the selected microcontroller.
• The extension requires some changes in the TAI
  unit.
• Current design should serve as a hardware
  platform for the IEEE 802.11 MAC.