CS2200 Presentation 2

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CS2200Presentation 2

• Processors

2
Our Road Map
Processor
Memory Hierarchy
I/O Subsystem
Parallel Systems
Networking
3
Five Classic Components
Processor
Memory
Control
Datapath
4
What does the processor do?

• Knows where it is in program
• Can get and put data into memory
• Can do some arithmetic
• Can make tests and take different paths depending
  on the results
• Do you need a language to make a computer run?

5
A Little History
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A Little History
7
A Little History

• First computers programmed by hand
• 1000110010100000
• Somewhat tedious, so invented
• Assembler
• add A,B
• If we can convert from Assembly Language to
  machine code why not from some higher level
  language to Assembler?
• A B

8
Back to the Instruction Set Architecture

• 1000110010100000
• Why study at this level?
• Common focal point

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Instruction Set Architecture
C
Fortran
Ada
etc.
Basic
Java
Compiler
Compiler
Byte Code
Assembly Language
Assembler
Interpreter
Executable
HW Implementation 1
HW Implementation N
HW Implementation 2
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Instructions

• Language of the machine
• Vocabulary is the instruction set
• Two levels
• Human readable
• Machine readable
• Most are similar
• What are the goals?

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Processor Design Goals
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Beyond LC

• Influences on Processor Design
• Cost of hardware
• Cost of memory
• Sophistication of compiler and language design
• Real world experience
• Design techniques/collaboration

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Instruction Set Classification

• One way
• Number of operands for typical arithmetic
  instruction
• add s1, s2, s3

• What are the possibilities?
• Will use this C statement as an example
• a b c
• Assume a, b and c are in memory

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Zero Address Machine
0

• a.k.a. Stack Machines
• PUSH b Push b onto stack
• PUSH c Push c onto stack
• ADD Add top two items
• on stack and replace
• with sum
• POP a Remove top of stack
• and store in a

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One Address Machine
1

• a.k.a. Accumulator Machine
• One operand is implicitly the accumulator
• LOAD b ACC ? b
• ADD c ACC ? ACC c
• STORE a a ? ACC

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Two Address Machine
21

• a.k.a. Register-Memory Instruction Set
• One operand may be a value from memory (unlike
  Mips)
• Machine has n general purpose registers
• 0 through n-1
• LOAD 1, b 1 ? Mb
• ADD 1, c 1 ? 1 Mc
• STORE 1, a Ma ? 1

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Two Address Machine
22

• a.k.a. Memory-Memory Machine
• Another possibility do stuff in memory!
• These machines have registers used to compute
  memory addresses
• MOVE a, b Ma ? Mb
• ADD a, c Ma ? Ma Mc

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Two Address Machine
23

• a.k.a. Load-Store Instruction Set or
  Register-Register Instruction Set
• Typically can only access memory using load/store
  instructions
• LOAD 1, b 1 ? Mb
• LOAD 2, c 2 ? Mc
• ADD 1, 2 1 ? 1 2
• STORE 1, a Ma ? 1

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Three Address Machine
3

• a.k.a. Load-Store Instruction Set or
  Register-Register Instruction Set
• Typically can only access memory using load/store
  instructions
• LOAD 1, b 1 ? Mb
• LOAD 2, c 2 ? Mc
• ADD 3, 1, 2 3 ? 1 2
• STORE 3, a Ma ? 3

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History
Hardware Expensive Memory Expensive Accumulators
EDSAC IBM 701
Hardware Less Expensive Memory Expensive Register
Oriented Machines (2 address) Register-Memory
IBM 360 DEC
PDP-11 Also Fringe Element Stack Machines
Burroughs B-5000 (Banks)
Hardware and Memory Cheap Microprocessors Compile
rs getting good CISC VAX
Motorola 68000 Intel
80x86 RISC Berkley RISC?Sparc
Dave Patterson Stanford MIPS ?SGI
John Hennessy IBM 801
1940 1950
1960 1970
1980 1990
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Questions?
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AddressingModes
How is the location of the operand is encoded
into the instruction?
circa 1975
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Recall the LC-3

• Immediate - Operand is in the instruction
• Register - Register number is in instruction
• PC-Relative - Offset which must be added to PC is
  in the instruction
• Indirect - Specified location contains an address
  as opposed to the operand
• Base Offset - Both a register number and an
  offset are contained in the instruction

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Questions?
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What do we have to support?

• What constructs in C must we be able to convert
  into executable code?

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Typical Operation

• add a,b,c a b c
• What if we want to do a bcde?
• add a,b,c
• add a,a,d
• add a,a,e

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Whats the answer?

• (56) - (34)
• How did you do it?
• e (ab) - (cd)
• add t1,a,b
• add t2,c,d
• sub e,t1,t2

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Operands

• add a, b, c
• Where are a, b and c?
• Memory?
• I/O Device?
• Registers (in processor)?
• ???
• How does the data get in and out of the
  registers?
• load
• store

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Common Operations

• g h A8
• load s0,8(s3)
• actually
• lw s0,8(s3) lw dest, offset(base)
• add s1, s2, s0 add dst, src1, src2
• Notice Registers contain data or addresses!!

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Why lw not load

• The byte (8 bits) is very useful so most
  architectures support byte operations.
• (The LC2200 does not!)
• Thus, each byte has an address.
• However, for efficiency, a 32-bit machine can
  also move 4-byte words around.
• Thus, each word has an address
• Typically word addresses are multiples of ?
• Unfortunately, this leads to...

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Endianess

• No, were not making this up.
• at word address 100 (assume a 4-byte word)
• long a 0x11223344
• big-endian (MSB at word address) layout
• 100 11 22 33 44
• 0 1 2 3
• little-endian (LSB at word address) layout
• 11 22 33 44 100
• 3 2 1 0

Who cares?
32

• string layout starting at word addr 100
• char a12 RAMACHANDRAN
• char b12 WAMACHANDRAN

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Perception Check

• What exactly are we doing?
• HLL (C) ? Assembler
• Assembler ? Machine Instructions
• Goals
• See how HLL translate to Assembler
• Understand hardware designs, constraints, goals,
  etc.

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Slightly more complex

• A12 h A8
• Compile it?
• lw s0, 8(s1)
• add s0, s2, s0
• sw s0, 12(s1)

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Historical Note

• Early machines often had a register called an
  index register
• load addr(index)
• Address space was small
• Today
• lw s1, offset(base)
• Base address are much larger...need to be in a
  register
• Often offsets are small but if not...

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Variable Array Index?

• g h Ai
• add t1, s2, t0 i addr(A)
• lw t2, 0(t1) a1 ? Ai
• add s0, s1, t2 g ? h Ai

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How many registers?

• Early machines had about 1 (Accumulator)
• PDP-11 series had 8
• Typical 32 bit processors today have 32 or more!
• Why not more?
• What happens when there are more variables than
  registers?
• Spillage Putting less commonly used variables
  back into memory.

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Factoid

• accumulator Archaic term for a register. On-line
  use of it as a synonym for register is a fairly
  reliable indication that the user has been around
  for a while.
• Eric Raymond, The New Hackers Dictionary, 1991

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Note the speed

• Register ops access two regs and perform an
  operation
• Memory ops access one location and dont do
  anything to it!
• What do you think about the speed of memory
  versus registers?

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LC2200-8 Registers
Name
R
Usage
Preserved on Call
zero
0
The constant value 0
n.a.
at
1
Reserved for assembler
n.a.
v0
2
Return value
no
a0-a2
3-5
Arguments
no
t0-t2
6-8
Temporary general purpose registers
no
s0-s2
9-11
Saved general purpose registers
yes
k0
12
Reserved for OS/traps
n.a.
sp
13
Stack pointer
yes
pr
14
Page Register
yes
ra
15
Return address
yes
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Decisions, decisions...

• What distinguishes a computer from a simple
  calculator is its ability to make decisions.
  Some smart guy.
• Typical implementation
• Branch if equal
• Branch if not equal
• Sometimes check one value (register) versus 0,
  others compare two items (registers)

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if statement

• if (i j) goto L1
• f g h
• L1 f f - i
• beq a0, a1, L1 if ij goto L1
• add s0, s1, s2 f g h
• L1 sub s0, s0, a0 f f - i

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Did we just use a go to???
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if statement

• if (i ! j)
• f g h
• f f - i
• beq a0, a1, L1
• add s0, s1, s2
• L1 sub s0, s0, a0

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if-then-else

• if (i j)
• f g h
• else
• f g - h
• beq a0, a1, Then if opp is T
• add s0, s1, zero f g h
• beq zero, zero, Exit
• Then add s0, s1, s2 f g h
• Exit

The LC2200 has no BNE
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Loop with Variable Array Index
reg
contents

• Loop g g Ai
• i i j
• if (i ! h) goto Loop

s0
g
s1
h
s2
i
a0
j
Loop add t0, s2, a1 lw t0,
0(t0) add s0, s0, t0 add
s2, s2, a0 beq s2, s1, Exit
beq zero, zero, Loop Exit
a1
addr of A
t0
temp
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While Loop

• while (savi k)
• i i j
• Loop add a1, s1, s0
• lw a2, 0(a1)
• beq a2, a0, Skip
• beq zero, zero, Exit
• Skip add s1, s1, s2
• beq zero, zero, Loop
• Exit

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Case/Switch

• switch (k)
• case 0 f i j break
• case 1 f g h break
• case 2 f g - h break
• case 3 f i - j break
• slt t3, s5, zero If k lt 0
• bne t3, zero, Exit Exit
• slt t3, s5, t2 If k gt 4
• beq t3, zero, Exit Exit
• add t1, s5, s5 mpy k by 4
• add t1, t1, t1

Mips
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Case/Switchcontinued

• switch (k)
• case 0 f i j break
• case 1 f g h break
• case 2 f g - h break
• case 3 f i - j break

Jmptbl Address(L0) Address(L1) Address(L2)
Address(L3)
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Case/Switchcontinued

• switch (k)
• case 0 f i j break
• case 1 f g h break
• case 2 f g - h break
• case 3 f i - j break

add t1, t1, t4 t1 Jmptabk lw t0,
0(t1) jr t0 jump based
on reg t0 L0 add s0, s3, s4 j
Exit etc...
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Questions?
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