Production Readiness Review of the MDT ROD

1
Production Readiness Reviewof the MDT ROD

• Electronic Design Details

2
MROD-X Design, Changes with respect to the MROD-1
design
MROD-1
MROD-X
3x

SHARC links used for data transport
RocketIO links used for data transport
3
RocketIObetween MROD-In and MOD-Out FPGAs
MROD-Out FPGA
MROD-In FPGA
Event Data
Event Data
FIFO 8191
FIFO 511
RdRq
1.6 Gb/s (160 MB/s)
HF
Event Length (ID)
Event Length (ID)
FIFO 511
FIFO 511
RdRq
HF
Rocket IO
Rocket IO
Regis- ters
Regis- ters
Extended Return Data
Extended Return Data
FIFO 511
FIFO 511
Return Data
Return Data

• Backpressure
• 8B/10B
• Extended Data
• Length Look-ahead
• TDC Limit

High Priority Path
Connections from other 7 MROD-In FPGAs
Low Priority Path
4
TDC Limit Register
D 1
D 2
D 3
D n
B O T
E O T

TDC Word Count bits 110
n
12 bit, programmable 1 to 4096 data words
Example when limit is set to 4

• Register default 0x60
• Maximum Event Fragment
• for 18 TDCs
• 18 x (BOT 96 1 EOT)
• 1782 words

D 5
D 4
D 1
D 2
D 3
B O T
E O T
D 4
D 1
D 2
D 3
B O T
E O T
6
7
D 4
D 1
D 2
D 3
B O T
E O T
D 4
D 1
D 2
D 3
B O T
E O T

• MROD-Out, Event Builder
• Maximum Event Fragment
• 8 x (1782 4 envelope words)
• 14288 words

6
7
No shutdown as with Maximum Event
Length (Default 1K words)
5
Backpressure and ROD-Busy
MROD-In Buffer Memory Partition
RocketIO FIFOs
S-Link FIFO
MROD-Out Event Builder
MROD-In Output Controller
CSM link
18x 8k
8x 8K
1x 511
X
Link FIFO Full
Half Full
Almost Full

• ROD-Busy
• Backplane P3 -gt TIM
• Front panel NIM
• Front panel Led

Up
Busy
Error
When one of 18 partitions Half Full Or I2O-FIFO
Half Full then CSM Link Busy Front panel Led B
I2O FIFO 512
I2O-FIFO event fragment complete -gt start
MROD-In Output Controller
Half Full
MROD-In Buffer Memory Partition 8K
words Consider the situation where a lot of small
events are received. Buffer Memory Partition does
not get Half Full while I2O-FIFO rapidly
fills. I2O FIFO Half Full signals ROD-Busy.
6
TTC FIFOs
Other busy sources

• ROD-Busy
• Backplane P3 -gt TIM
• Front panel NIM
• Front panel Led

HF
Event/Bunch-ID FIFO 511
TTC4 Event/ Bunch-ID
De Serialize
Event Builder
HF
Trigger-Type FIFO 511
Load
Extended Event-ID
Inc
De Serialize
P3 backplane driven by TIM
TTC5 Trigger Type
Event/Bunch-ID FIFO 511
MROD-Out SHARC
DMA
Trigger-Type FIFO 511

• Debug
• Test
• Monitor

TTC1 ECR
MROD-Out FPGA
7
Event Builder (1)
Event Fragment Header
TTC FIFOs not empty
Event Builder
2
1
Event Data
Test Count Event-ID
RocketIO 1A
3
Test Mode
Event Length

• Wait for TTC info
• Send Header
• Repeat
• If a channel is enabled (wait for / read) event
  length entry
• then read event data and insert Link Word Count
• Until all channels read
• Send Trailer

1A Busy
8 x
4
Channel Enable Register
Event Data
RocketIO 4B
5
Event Length
Event Fragment Trailer
4B Busy
ROD-Busy
8
Event Builder (2)

• Event Fragment Header
• BOF (S-Link Control Word) 0xB0F00000
• Header Marker 0xEE1234EE
• Header Size 0x00000009
• Format Version Number (VME register) 0x03000000
• Module ID (VME Register) 0x00610080
• Run number (VME Register) 0x00000000
• Event ID 0xEEeeeeee
• Bunch-ID 0x00000bbb
• Trigger-Type 0x000000tt
• Detector Event Type (VME Register) 0x00000000
• MROD BOB 0x80eeeeee

Test Mode Normal Running eeeeee from TTC Test
Mode (run without TTC) eeeeee from Test Counter
TDC Event-ID Miss Match

• Event Fragment Trailer
• MROD EOB 0xF000wwww
• MROD Status word (MSE1)
• Number of Status Elements (NSE) 0x00000001
• Number of Data Elements (NDE) 0x0000wwww
• Status Block Position 0x00000001
• EOF (S-Link Control Word) 0xE0F00000

TDC Bunch-ID Miss Match
20
31-21
19
18
17
16
15-4
3
2
1
0
TDC Parity Error
GOL Parity Error
9
Spy (MROD-In)
MROD-In FPGA
Event Data FIFO 512
SHARC
AF
Event Length FIFO 16

• Debug
• Test
• Monitor

AF

• Spy Pre-scale register
• No
• All
• One in n 1..65536

1. MROD-X Mode
2. MROD-1 Mode
3. MROD-X Debug

Event Data FIFO 8191
MROD-In Output Controller
AF
Event Length FIFO 511
Rocket IO
AF
By Default Main data stream is not halted by Spy
Channel
10
Spy (MROD-Out)
MROD-Out FPGA
Event Data FIFO 16K
SHARC
AF
Event Length FIFO 4

• Debug
• Test
• Monitor

AF

• Spy Pre-scale register
• No
• All
• One in n 1..65536

1. MROD-X Mode
2. MROD-1 Mode
3. MROD-X Debug

S-Link FIFO 511
AF
Event Builder
By Default Main data stream is not halted by Spy
Channel
11
Test Generator
MROD-In
(Pre-scaled) Data and Event-Length
MROD_In Functionality
SFP
RocketIO
Test FIFO
External Loop back
SHARC
SHARC Links
FPGA
(Pre-scaled) Data and Event-Length
MROD_In Functionality
SFP
RocketIO
Test FIFO
FPGA

• CSM links unidirectional
• Test generator
• Transparent / Circular mode
• Free running / Triggered
• Internal test mode

TTC L1A
12
Remote Configuration (1)FPGA JTAG Chain
Geographical Address
J26
XCF08P
ASP
MRO_XCF08P_TDI
Configuration Bus
MTM bus
MROD-Out
FPGA_TDO
Xilinx XC2VP20
TDI
TDO
SelSharcF for 3 or 4 MROD-Ins
XCF08P
FPGA_TDI
Configuration Bus
Xilinx XC2VP7/20
Xilinx XC2VP7/20
Xilinx XC2VP7/20
Xilinx XC2VP7/20
Xilinx XC2VP7/20
Xilinx XC2VP7/20
Xilinx XC2VP7/20
Xilinx XC2VP7/20
FPGA_TDO4
FPGA_TDO3
MROD-In FPGAs
13
Remote Configuration (2)
to all MROD modules
MTM bus
P1
buffers
buffers
P2
USB-JTAG ( Xilinx Download Cable)
P3
rear
front
VME bus
14
Other Extras
FPGA firmware Date and Revision
Register Automatically determined during
synthesis of VHDL code (TCL script)
OS Date
Rev. File
31-24
23-16
15-8
7-0
Year
Month
Date
Revision
Unique Identifier Registers (DS2401)
31-24
23-16
15-8
7-0
ID1
ID31-0
ID2
Family-ID
CRC
ID47-32
Temperature Readout for each FPGA (MAX 1618)

• Zero Suppress Override
• choose to override zero suppression
• Never
• Once every n 1..65536 events (first event of
  a run always non zero suppressed)

S-Link Flush Mode
15
Production Readiness Reviewof the MDT ROD

• Prototype issues

16
Design issues found in prototypes

• Parallel termination for MROD-In FPGA
  configuration bus
• Pull-up resistor on FPGA TDO
• Wrong polarity for two capacitors
• Small errors in silkscreen (Dip switch SW9, Ref.
  IC511, Pin 1 marking)
• Footprint for inductors too small
• Short pin 1-2 for SMD LEDs (2 Anode, 3
  Cathode)
• Power On Reset circuit TPS3838

1
2
2
1
SOT23
SOT23
3
3
MR pin 3
Okay
Fail
Rst_n pin 4
VDD pin 1,5
Critical Ramp-Rate 125 mV/ms Happens to be
exactly VME crate power supply Ramp-Rate!
17
Minor Assembly issues found in prototypes
Assembly house did a great job. Some issues

• One capacitor misplaced (module 1)
• Software Test Procedure found 2 open address pins
  on a Temperature Sensor (module 1)
• One wrong component placed. IC511 NC7SZ125
  instead of NC7SZ126 (module 3)
• One IC557 missing (NC7SZ08) (module 5)
• One wrong component placed. IC564 NC7SZ08
  instead of NC7SZ126 (module 5)
• Open output pin on buffer, SHARC JTAG chain
  (module 6)

Automatic Optical Inspection would track many, if
not all of these failures.
Keep in mind that we asked for assembly of 6
modules (4 different production runs) 2
eight-channel, 1 eight-channel, 1 eight-channel
without SHARC-B, 2 six-channel
18
Changes to be made in PCB

• Needed
• Parallel termination for MROD-In FPGA
  configuration bus (add 18 resistors)
• Add Pull-up resistor to FPGA TDO
• Change the polarity for two capacitors
• Connect pin 1 and 2 for SOT23 SMD LEDs
• Increase Footprint for inductors
• Power On Reset (still under investigation Use
  MAX 6863?)

• Needed for MROD-Out _at_ 50 MHz
• Review Clock circuit on MROD-Out
• Remove automatic Clock switch for selection of
  LHC-Clock or crystal
• Re-route one LHC-Clock signal
• MROD-Out FPGA prepared, system operation still to
  be demonstrated

• Desirable
• Inverter for GA4..0 connected to ASP
• Review silkscreen (SW9 and IC511, Pin 1 marking)

19
Thank you
20
MROD_In
MROD_Out
Xilinx XC2VP7/20
SFP
SHARC
SHARC A
GOL_XClkA
Sharc Clk
Rocket XClkA
ChA_Clk
ChA_Clkx2
Rocket XClk
ZBT
80
Xilinx XC2VP20
50/80
80
Robo Clock
Clk
Clkx2
LHC_Clk
ZBT
ChB_Clk
SHARC B
Rocket XClkB
ChB_Clkx2
LHC_Clk1
GOL_XClkB
40
40
Sharc Clk
Xilinx XC2VP7/20
SFP
Robo Clock
LHC_CLk2
MROD_In
Robo Clock
LHC_Clk (From TIM)
LHC_Clk3
MROD_In
LHC_Clk4
MROD_In
S-Link
MROD-X Clocks
21
MROD_In
MROD_Out
Xilinx XC2VP7/20
SFP
SHARC
SHARC A
GOL_XClkA
Sharc Clk
Rocket XClkA
ChA_Clk
ChA_Clkx2
100
ZBT
Rocket XClk
100
Xilinx XC2VP20
50/80
Robo Clock
Clk
Clkx2
LHC_Clk
ZBT
ChB_Clk
50
SHARC B
Rocket XClkB
ChB_Clkx2
LHC_Clk1
GOL_XClkB
40
Sharc Clk
Xilinx XC2VP7/20
Robo Clock
SFP
X
Robo Clock
LHC_CLk2
MROD_In
LHC_Clk (From TIM)
LHC_Clk3
MROD_In
LHC_Clk4
MROD_In
S-Link
MROD-X Clocks (MROD-Out _at_ 50 MHz)