SIT Stuff for SEP Peer Review

1
SIT Stuff for SEP Peer Review

• 19 Apr 2001

2
Telescope

• TOF vs E
• FOV
• Energy - 1 SSD
• surface barrier or ion implant
• 15mm x 40 mm
• 500u
• TOF - 1 START 1 STOP
• 10 cm flight path
• chevron pair micro-channel plates
• 1000v bias per plate, commandable
• Foils - 2
• Ni
• 1000A, on grid

3
(No Transcript)
4
(No Transcript)
5
BLOCK DIAGRAMS
6
SIT - Box-Level Block Diagram
Actuator power
SUNSHADE
COVER ACTUATOR
TEST CONNECTOR
TELESCOPE
SIT ELECTRONICS
SSD Signal
Data Control
LV Power
START
SSD Bias
STOP
Power
HV Control
SIT HVPS
HV Bias
7
SIT BLOCK DIAGRAM
Unlatch
Cover
Board 1
UMd/Caltech
Energy Electronics Logic/MISC/CPU IF
TELESCOPE
To/From CPU
Caltech/GSFC
Board 2
UMd/GSFC
TOF Analog Electronics
Board 3
MPAe
TOF Digital Electronics
GSFC/UMd
Motherboard
UCB
HVPS
TEST CONNECTOR
LV Interface
Low Voltages
SSD Bias
Housekeeping
SIT
8
SIT FUNCTIONAL BLOCK DIAGRAM
Actuator Control
SSD Bias
Cover Actuator
Energy
Commands
SSD
Energy Data
VLSI
Event Data
Front- End Logic
To SEP CPU
MISC
Commands
Disc
Coincidence
(ACTEL)
START
TOF Data
TELESCOPE
TOF
Clk
STOP
TOF Calibration Singles Rates
Test Connector
From LVPS
LV
HVPS
HV
From Bias LVPS
SSD Bias
HV Control
9
SIT ENERGY SYSTEM BLOCK DIAGRAM
Caltech VLSI
CONFIG DATA
Configuration Electronics
150-200v
6
One Section of 10
SERIAL DATA
Amptek A250
High Gain Channel
CSA
2N6550
CONTROL
Coupling Network (TBD)
Read Out Electronics
SSD
Low Gain Channel
DISC.s
Test Input
Remaining 9 sections unused, unpowered
(6,-6)
Regulation
(5, -5)
6
12
-6
-12
-5
10
SIT TOF BLOCK DIAGRAM
ANALOG SECTION
Digital Section (TUB)
START
CUSTOM ASIC
ACTEL Gate Array
Constant- Fraction Disc.
Amplifier
SIGNALS FROM TELESCOPE
(Measures time-of-flight)
(Provides Necessary Control Interface Functions
)
SIGNALS TO/FROM SIT LOGIC CIRCUITRY
STOP
Test Connector
11
(Put TOF Schematics Here)- TOF amplifier- TOF
CFD
12
(No Transcript)
13
(No Transcript)
14
TOF DIGITAL BLOCK DIAGRAM
/START
3 /
Time-to- Digital Converter
SERIAL TOF DATA I/F
SERIAL RATE CALIBRATION DATA I/F
/STOP
3 /
(TDC)
10 MHz Clock
BUFFERS
RESET
/COINC
/E Discriminator
EVENT COUNTER
TDC Control Coincidence Check
I/F Control
5 3.3 -5
Main Control
Latch Up Protection
PWRSTAT
15
Front-End Logic Tasks

• Collect Events and present them to MISC
• Receive Commands from MISC and Execute them
• VLSI initialization and control
• HV control (Digital to Analog conversion)
• Provide 10MHz clock for TOF Circuit

16
ACTEL
Data
To Energy VLSI
VLSI Readout Circuitry
Control
Event Buffer
Data
Data
To MISC
TOF Readout Circuitry
To TOF Digital
Control
/Coinc
Flag
Data Ready
Control Logic
/DatWR
VLSI Initialization
Command Circuitry
10 MHz Clock for TOF
SIT Front-End Logic Block
DAC
HV Control
17
Wait for Coincidence
Read out Energy PHA from VLSI
Wait for TOF /DatWR Signal
Store Energy PHA in Event Buffer
Read out TOF PHA from TOF ACTEL
Store Ramp Bit in Event Buffer
Store TOF PHA in Event Buffer
Signal EVENT READY
SIT Event Pre-Processing in Front-End Logic
Transfer EVENT
Done
18
MISC Tasks

• Initialization of Self and VLSI
• Power-on reset
• External reset from SEP CPU
• Watchdog timer?
• Event Processing
• Event binning/matrix rate counting
• Event prioritization and storage
• TOF Calibration
• Singles Rate Collection (counting done in TOF)
• Command Processing
• Output data Formatting and Transmitting
• rate compression
• buffer management
• output data to SEP CPU

19
Event Data
Serial Port to CPU
FRONT-END LOGIC
Commands
MISC
TOF Calibration Singles Rates
TOF Digital Board
MISC BLOCK DIAGRAM
RAM
20
Rate gt128?
Collect Event
Yes
Priority?
Hi
Lo
Add 4-bit sub-frame count to LS 4 bits of Rate
Number
No
E (11 bits) T(8 bits) Range Bit
Hi Priority Buffer Full?
Lo Priority Buffer Full?
Add Ping/Pong Offset to Rate To get Rate Address
Look up log T in T lookup table
Store Event in Hi Pri Buffer
Store Event in Lo Pri Buffer
Increment Matrix Rate
Range Bit?
1
0
Increment Hi Priority Buffer Counter
Increment Lo Priority Buffer Counter
Range Bit?
1
0
Look up log E in High Gain E lookup table
Look up log E in Low Gain E lookup table
Done with Event
Rate Number 288
Rate Number 304
Generate Offset into Rate Number table from logE
logT
Add 4-bit sub-frame count to LS 4 bits of Rate
Number
Look up Rate in Rate Number Lookup table
SIT EVENT PROCESSING
Add Ping/Pong Offset to Rate To get Rate Address
Extract Store Priority Bit from Rate Number
Increment Matrix Rate
21
HVPS

• Provides bias voltages to operate the
  microchannel plates and to focus the secondary
  electrons produced by incoming ions
• Nominal voltages 3400,3200,2200,2000,1000 and
  950 v
• Top voltage controlled by command, others change
  proportionally
• 0-5v control voltage
• Maximum output 4200v
• On/Off Command 5v level
• Disable plug to prevent operation during ground
  testing
• Operates on /- 12v
• Supplied in housing by UCB

22
Board Outlines
23
10 cm
Mounting Holes TBD
CM860 FET
SSD In
Nanohex (2)
ACTEL 54SX CQFP208
A250
TC In
E BOARD Logic (Top Side)
36 x 36 x 2 mm, 13g
37-pin prewired Plug
Shield?
10 cm
6g
N10138/201-37
CALTECH VLSI
40 x 40 x 4 mm ? g
Clock
Clk
A250
Shield?
VLSI
Actel
1.0 cm
Memory
Actel
24
10 cm
Mounting Holes TBD
SSD In
ACTEL 54SX CQFP208
Keep-out Area
36 x 36 x 2 mm, 13g
TC In
E BOARD Logic (Bottom Side, Top View)
37-pin prewired Plug
10 cm
N10138/201-37
128k x 8 Memory, Cypress 32 pin TSOP, 20 x 8 mm
Clk
A250
Shield?
VLSI
Actel
1.0 cm
Actel
Memory
25
10 cm
Mounting Holes TBD
START In
START AMP 4.8 x 3 x 0.6cm
START CFD 6.2 x 3.6 x 0.7 cm
Nanohex (2)
TC In
TOF Analog BOARD
37-pin prewired Plug
/START
To TOF DIGITAL
10 cm
/STOP
N10138/201-37
6g
STOP AMP 4.8 x 3 x 0.6cm
STOP In
STOP CFD 6.2 x 3.6 x 0.7 cm
Nanohex (2)
TC In
Constant-Fraction Disc.
Amplifier
Input
1.0 cm
26
10 cm
Mounting Holes TBD
TUB Digital Electronics
TOF Digital BOARD
37-pin prewired Plug
10 cm
N10138/201-37
6g
TOF Digital Electronics
1.2 cm (TBD)
27
Motherboard
TOF Digital Electronics
Connector to HVPS
Constant-Fraction Disc.
Amplifier
3.6 cm
TOF Input
Shield?
SSD Input
Actel
Clk
A250
VLSI
Connector to SEP
Memory
SIT Electronics Assembly
28
5.4 cm
Connector to HVPS
3.2 cm
Connector to SEP
MOTHER BOARD
29
12 cm
TOF Digital Electronics
4.2 cm
Side View
Constant-Fraction Disc.
Amplifier
Shield?
Actel
Clk
A250
VLSI
Overall Size
TOP View
10 cm
30
Output Data

• PHA Events - 24 bits
• Energy 11 bits ramp bit
• TOF 8 bits
• Misc - 4 bits
• Singles Rates
• Matrix Rates
• Low time resolution
• High Time resolution
• Housekeeping
• Status (?)

31
Output Data Format

• TBD

32
Bit rates

33
Commissioning

• Turn ON LV with all of SEP - shortly after launch
• Open acoustic cover - TBD
• soon to prevent sticking
• late enough to avoid major periods (gt few
  seconds) of sun in FOV
• Put in Science Mode - turn on and ramp up HV
• conducted over several (e.g. 5) days
• requires commanding and data viewing during
  real-time pass each day
• Verify Proper Operation - observe/process
  science data

34
Commanding

• Commissioning Phase
• Power, cover, HV commands - several commands/day,
  several days
• Verification of Operation - few tens of commands
• Possible table upload to correct problems
• Science Mode
• Possibly a few commands/week to calibrate sensor
• No other periodic commands required
• Rarely a table upload to compensate for gain
  drifts or other problems

35
Purging

• Clean dry (bottled) GN2 will be used to purge SIT
  telescope during integration and test at UMd
• Continuous N2 purge of telescope required during
  instrument testing on bench and on S/C (with
  obvious exceptions for environmental tests).
• Purge on pad?
• SIT will be connected to SEP purge manifold and
  will purge at same time as rest of SEP.
• Flow rate TBD but 0.5 SCFH, Pressure TBD
• Special filters for particulates?
• Not required for SIT but necessary to meet
  cleanliness?

36
WHO DOES WHAT page 1 of 3
PROTOTYPE UNIT
37
WHO DOES WHAT page 2 of 3
FLIGHT MODEL UNIT 1
38
WHO DOES WHAT page 3 of 3
FLIGHT MODEL UNIT 2