Analog RF TopDown Design

1
Analog RF Top-Down Design

• Andrei Vladimirescu, Chinh Doan, Brian Limketkai,
  David Sobel, Johan Vanderhagen, Dennis Yee,
  Isabelle Telliez, Bob Brodersen

2
Outline

• Project Goals
• Desired Flow vs EDA Tools
• Levels of representation
• Implementation

3
Goals

• Start from design in technology N,
• design equations
• schematics
• layout
• Semi-automatic port to technology N1, N2, etc.
• Reduce time from system spec to tested chip
• Explore design space, trade-off curves
• Generate sized design from block-level diagram
• based on existing parameterized circuits

4
Constraints

• No CAE tool development
• only scripts to enable data flow among different
  tools
• Align if possible with ST design flow
• source for process parameters
• Re-use existing designs
• Challenge
• best tools in flow from different EDA suppliers

5
Past Experience

• Design Automation limited to specific circuits
• opamps, filters.
• Analog Synthesis is still a buzzword
• OPASYN (UCB), OASYS (CMU), IDAC (CSEM)
• Barcelona Design, Antrim
• Approach
• Hierarchical Decomposition
• Match topologies in library to performance spec
• Analysis eqn. Setup Simulation/Optimization

6
Desired Flow

• Co-design receiver w/ digital part
• Simulink
• Specification
• W-CDMA, f 2 GHz, BW 32 MHz
• Architectural Definition
• Direct-conversion, Equations, Design Variables
• First Optimize module parameters to Spec
• Matlab
• Generate block-diagram of receiver (behavioral)
• LNA, Mixer, PLL, ADC in Verilog-A

7
Desired Flow (Contd)

• Circuit specifications at behavioral level
• complex blocks, PLL, ADC, into components
• detailed performance equations - small-signal
  (Verilog-A)
• Match transistor circuits to behavioral
  description
• W/L dimensioning
• Second Optimize W/L to match behavioral model
• Iterate at SPICE-level
• both behavioral and transistor-level

8
Mapping Representations to Design Tools

• Functional simulation
• Simulink/Matlab top-level functional model
• Spec characteristics gain, NF, etc.
• SPICE-level simulation
• Behavioral model (Verilog/VHDL AMS, MAST, C)
• Detailed small-signal analysis description, e.g.
  compression point, IP3
• Transistor-level, detailed circuit
• DC bias
• Combine descriptions for optimal thruput/accuracy
• Electrical to Physical (Layout)

9
Design Continuum over Tools

• Levels of representations
• Matlab
• Simulink
• Verilog-A
• Xtor Schematic
• Layout

Same Simulator
Same Parameters
Same Simulator
Same Parameters
10
Explore Design Space

• Design equations
• top-level linked to individual blocks
• Quick but accurate trade-offs
• global performance vs. per block
• Simple but accurate transistor models
• e.g. EKV

11
Analog CMOS Design Requirements

• Low-power
• minimize VGS-VT
• High gain
• minimize VGS-VT
• Maximize output excursion/Constant current
• bias at limit of saturation
• Operate Xtor at limit of Subthreshold
• gm/IDS is key design variable

12
gm/IDS
13
gm/IDS of simplified EKV
14
Receiver Characteristics -gt Optimized Modules

• Noise vs. Distortion
• Optimization variables I/W and W for each block
• Optimization in Matlab to generate per block
  performance
• Block characteristics used at the Verilog-A level
• Dilemma Need accurate design equations
• Imply known circuit topology

15
Alternate Module Performance Allocation

• Allocate performance numbers based on tables of
  characteristics for different circuit topologies
• Design circuits to spec using optimization
• Derive equations for the chosen architecture
• Return to first step and optimize
  allocation/design
• Collect equations in design library

16
Levels of Representation

• Choice of detail at each level critical for
• design performance
• design cycle
• simulation time
• iterations
• Example PLL

2 GHz
Mobile Receiver
ADC
I
LNA
Q
ADC
PLL
17
Simulink View of PLL
18
Next level down - Verilog-A

• Behavior expressed in Language
• Performance parameters are identified
• Design Equations are captured
• Implementation still missing
• Simulation control
• Same accuracy as transistor-level blocks
• Can control accuracy of models
• sometimes lacking in nonlinearity/charge storage
• Can combine Verilog-A blocks with Xtor circuits

19
Example PLL

• PLL module
• include discipline.h
• module PLL(RF, LO, out)
• electrical RF, LO, outparameter real lpf_fc,
  lpf_gainparameter real vco_kv,
  vco_fc electrical IF PD pd(LO, RF, IF)
  LPF ( .fc(lpf_fc), .gain(lpf_gain )) lpf
  (IF, out) VCO ( .conv_gain(vco_kv),
  .fc(vco_fc )) vco (out, LO)endmodule

20
Example Contd

• Phase Detector
• include discipline.h
• module PD(LO, RF, IF)
• electrical LO, RF, IF inout LO, RF, IF analog
  V(IF) lt V(RF)V(LO)
• endmodule
• Voltage-Controlled Oscillator
• include discipline.h
• include constant.h
• module VCO(in, out)
• inout in, out electrical in, out
• parameter real conv_gain 1.0
• parameter real fc 1.0k analog V(out) lt
  sin( 2M_PIidt( fc conv_gainV(in), 0) )
• endmodule

21
Speed Improvement Example

• Simulink simulation time lt 2 min
• SpectreRF simulation time 1-2 hr

22
Automating Design - Optimization

• Parameterized Schematics in W,L
• same parameters in cell layout
• Optimization performed in SPICE simulator
• Performance goal, min/Max/function
• Constraints on geometries
• Key to recalibrate design in new technology

23
Circuit-level Optimization

• Performance Functions (Goals)
• Power P -gt minimize
• Noise vn2 -gt match spec
• Gain av _at_ fbaseband -gt match
• Distortion HD3 -gt match
• Define a weighted overall performance
• Goal a vn2 b av gP d HD3

24
Circuit-level Optimization

• Perform Sensitivity analysis for each Goal
• Pick most sensitive
• Define optimization variables
• W, L of transistors with most impact on Goal
• Set constraints on optimization variables
• Monitor each Goal and select preferred combination

25
Layout

• Most challenging
• parameterization linked to rectangles rather than
  module
• No automatic place/compaction from initial layout

26
What we have - Circuits

• Behavioral Equations (Matlab/Simulink)
• Base-line Verilog-A RF module library (Cadence)
• Circuit schematics
• LNA, mixer, PLL, A/D, D/A
• 2 GHz
• 0.25u ST CMOS
• Layout

27
What we have- Simulators

• Spectre
• Verilog-A, RF analysis, MOS9
• - Optimization stand-alone (available from
  Artist, Ocean)
• ADS
• Simulink tie-in, RF analysis, MOS9,
  optimization
• ? Robustness of Spice
• HSPICE
• Optimization
• - No behavioral, RF

28
Suggested Start

• Develop module library
• AC small-signal equations
• Encapsulate in parameterized behavioral blocks
• Xtor circuit schematics
• Process files for different technologies
• Experiment with two options
• ADS
• Spectre (optimization in Artist, generate Ocean)

29
To Do

• Define transition Simulink -gt behavioral module
• Single block in Simulink -gt block-diagram
  architecture in behavioral, Or,
• one-to-one block diagram with more detail in
  behavioral
• Define hierarchy for each module
• Define parameters at each level
• Define control SW for simulation launches

30
Conclusion

• A semi-automatic design flow for RF front-ends
• EDA tools identified for each level
• Examples of circuit block descriptions
• Need closure on
• detail at each level
• trade-off very accurate equations vs optimization
• Major challenges
• Design equation derivation
• Communication among diverse EDA tools