Ernest Orlando Lawrence Berkeley National Laboratory - PowerPoint PPT Presentation

1 / 44
About This Presentation
Title:

Ernest Orlando Lawrence Berkeley National Laboratory

Description:

PSRR=sideband in dBc for 1V (0dBv) supply noise tone. Hybrid Linear-Switching Regulators ... (almost) pure digital implementation! Need to run PDM process *as ... – PowerPoint PPT presentation

Number of Views:69
Avg rating:3.0/5.0
Slides: 45
Provided by: gab145
Category:

less

Transcript and Presenter's Notes

Title: Ernest Orlando Lawrence Berkeley National Laboratory


1
High Average-Efficiency Power Amplifier
Techniques Jason Stauth, U.C. Berkeley Power
Electronics Group
2
Overview
  • Application Space Efficient RF Power Amplifiers
  • PA Fundamentals, Polar/ET Architectures
  • Challenges with Polar/ET
  • Research Directions
  • Direct Digital Modulation
  • Pulse-Density Modulation

3
Power Amplifier Fundamentals
Edge Constellation 3pi/8, rotated 8-PSK
4
Linear Power Amplifier (PA)
  • Active transconductance device
  • Input matched to previous stage
  • Output (antenna) impedancetransformed to
    increasepower gain
  • Small-signal model close to common source
    amplifier

5
Nonlinear PA
  • Active device operates as a switch
  • Approx LTV System
  • Voltage waveform constrained
  • (also consider current waveform)

constrained
unconstrained
constrained
Drain Voltage
Gate Voltage
  • Class-F
  • Frequency Domain
  • Impedance Design
  • Class-E
  • Time domain
  • Impulse Response design

-Class E/F ZVS Amplifiers, Kee et al., MTT 03
6
The Point
  • Nonlinear PAs cant do amplitude modulation
  • Linear PAs can do amplitude modulation, but are
    inefficient

7
Average Efficiency
constant bias current variable bias current
PA Class Class A Class B Nonlinear PA
Average Efficiency 0.78 / 9.2 14.46 18.21
8
Polar and Envelope Tracking Transmitters
  • Supply regulation synchronous with RF Envelope

-Raab et al. High efficiency L-band
Kahn-technique transmitter," MTT-S,
1998. -Hanington, et al. "High-Efficiency Power
Amplifier Using Dynamic Power-Supply Voltage for
CDMA Applications," MTT, Aug. 1999.
9
Polar Architecture
  • Many (most?) implementations dont use an
    efficient supply modulator ?
  • efficiency gains from using nonlinear PA

10
Envelope Tracking
  • Linear (class-AB) PA
  • Efficient supply modulator (linear reg doesnt
    make sense)

Operate at max PAE point
11
Challenges
  • Bandwidth
  • Peak-average power ratio
  • Time alignment
  • Distortion (AM-AM, AM-PM)
  • PSRR

12
Project Directions
Wideband Switching Regulators
Hybrid Linear-Switching Regulators
Direct Nonlinear Modulation Transmitters
13
Wideband Switching Regulators
  • Envelope Tracking Architecture
  • Wideband 20MHz Envelope bandwidth
  • High switching frequency
  • High PSRR PA

14
Challenge Power Supply Rejection
  • Supply noise can mix into the RF spectrum,
    degrading SNR, violating spectral masks (ACPR)
  • New Concept design for high PSRR

-Stauth, Sanders, "Power supply rejection for RF
amplifiers," (RFIC) Symposium, June 2006
15
Results MTT Oct 07
  • Supply-Signal mixing term

PSRRsideband in dBc for 1V (0dBv) supply noise
tone
16
Hybrid Linear-Switching Regulators
17
Hybrid Regulator Paradigm
Parallel (shunt) Hybrid
Series Hybrid
  • Decouple bandwidth-efficiency (audio, AVS
    digital, PA supply)
  • Fast linear block (supply dynamic output
    voltage, attenuate switching regulator harmonics)
  • Slow switching block (efficient, low cost)
  • Series hybrid drawbacks low Vdd efficiency,
    headroom issues

18
Parallel Hybrid Operation
  • Linear Stage Voltage Follower (Class AB LDO)
  • Switching Stage Current source
  • Traditional
  • Previous work Optimize in the frequency domain

-Yousefzadeh, et al. ISCAS 05, PESC 06. -F. Wang
et al, MTT-S, June 2004. -P. Midya et al. PESC,
00.
19
This Work Optimize in the Time Domain
  • Fundamental many signals may share same power
    spectrum
  • Phase of signals not represented ? can be
    critical for max efficiency in the time domain
  • Consider strong nonlinearities in conversion from
    Cartesian to polar representation

PAPR10.1 dB
PAPR5.2 dB
20
Interesting Conclusions
Sin-AM, 2-Tone
IS-95 CDMA
  • Traditional method with
    is suboptimal
  • Optimum isr is a function of Vdd, and dynamics of
    the modulation signal
  • Power savings potentially very large for high
    PAPR signals, high Vdd

21
Future Work
  • Adaptive optimization
  • Performance tuning

22
Digital Pulse-Density Modulation
23
This work1-Bit Linear Transmitter
  • PA at max power or off
  • Inherent linearity
  • Improved efficiency in power backoff

24
Pulse Density Modulation Process
  • AM process ? Extra harmonics
  • Tradeoff between oversampling ratio Q
  • Out of band spectrum
  • Efficiency
  • Noise shaping digital ??
  • Conclusions
  • No major efficiency advantage with Qlt5-10
  • Linearity may be the compelling factor
  • (almost) pure digital implementation!
  • Need to run PDM process as fast as possible

Filter profile
Carrier with DSB harmonics
Power spectrum
25
PDM Process
  • Sigma-delta
  • Error feedback
  • Spectrum
  • bandpass in nature
  • Amplitude modulation
  • Noise Shaping

26
PDM Process
  • Modulate at fraction of carrier frequency ? out
    of band harmonics

27
PDM Process
  • Modulate at fraction of carrier frequency ? out
    of band harmonics

28
PDM Process
  • Modulate at fraction of carrier frequency ? out
    of band harmonics

29
Class-D PA
  • Conventional timing, control
  • Series-Resonant Filter ? block out of band
    harmonics
  • High impedance out of band ? reduce power drawn
    from supply for wasted energy

30
Architecture
  • Cartesian Representation
  • Noise-Shaped PDM amplitude modulation
  • Independent I-Q processing/upconversion
  • Class-D PA
  • Series resonant bandpass filter/transformer

31
Behavioral Verification
  • Ideal Components, PDM process
  • Passive network Q30
  • Vdd1.0V (assume 90nm CMOS)

32
Ideal ? no losses in switches, passives
33
Carrier Fundamental Linearity
  • Simulation, expt show good linearity vs pulse
    density
  • IM3 comparable to good linear PA (range of -20dBc
    to -40dBc)
  • Predistortion likely to improve linearity further

34
ClassD PA, 90nm CMOS, Spectre Sim, Q15 in
passives
35
2-tone test
36
Conclusions
  • Efficiency stays high in power backoff
  • Future analysis comparison of series resonant to
    parallel resonant output filters for class-D PAs
  • High linearity, compelling argument for this
    architecture

37
Implementation
  • Two chips
  • Modulator
  • Class D PA
  • Both 90nm CMOS,
  • Low voltage (1.0V),
  • Wirebond chip-on-
  • board

38
Architecture
  • Multiple stages RF PDM and Baseband sigma-delta
  • Tradeoff oversampling for power consumption
  • Still have 10-100x oversampling for most
    standards (edge, Bluetooth, WCDMA, 802.11x)

39
PDM Process
40
PA Blocks
  • Use 2.0V to drive for higher output power
  • Maximum Voxide1.0V
  • No resonant switching need accurate control of
    gate voltage
  • Recycle current used by high-side switches
    (excess goes to digital processing block)

41
Results
  • Program I/Q waveforms into FPGA
  • Downconvert/process signals with NI PXI box
    running labview
  • Results ? show linear downconverted I/Q waveforms

42
Two-tone spectrum
  • 10mV tones with 2MHz spacing at 1.95GHz carrier
  • 20MHz of noise shaping is functional, noise peaks
    50MHz from carrier at fs/2
  • LO leakage tuned with signal offset

43
802.11a, 64QAM OFDM Waveform
  • 10mV tones with 2MHz spacing at 1.95GHz carrier
  • 20MHz of noise shaping is functional, noise peaks
    50MHz from carrier at fs/2
  • LO leakage tuned with signal offset

44
References
  • 1 A. Jerng and C. G. Sodini, "A Wideband
    Delta-Sigma Digital-RF Modulator for High Data
    Rate Transmitters," IEEE Journal of Solid State
    Circuits, vol. 42, pp. 1710-1722, Aug. 2007.
  • 2 A. Kavousian, D. K. Su, and B. A. Wooley, "A
    Digitally Modulated Polar CMOS PA with 20MHz
    Signal BW," IEEE International Solid State
    Circuits Conference (ISSCC) Dig. Tech. Papers,
    pp. 78-588, 2007.
  • 3 S. M. Taleie, T. Copani, B. Bakkaloglu, and
    S. Kiaei, "A bandpass Delta-Sigma RF-DAC with
    embedded FIR reconstruction filter," IEEE
    International Solid State Circuits Conference
    (ISSCC) Dig. Tech. Papers, pp. 578-579, 2006.
  • 4 R. B. Staszewski, J. Wallberg, S. Rezeq,
    C.-M. Hung, O. Eliezer, S. Vemulapalli, C.
    Fernando, K. Maggio, R. Staszewski, N. Barton,
    M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad,
    and D. Leipold, "All-digital PLL and GSM/EDGE
    transmitter in 90nm CMOS," IEEE International
    Solid State Circuits Conference, vol. 1, pp.
    316-600, Feb. 2005.
  • 5 J. Lindeberg, J. Vanakka, J. Sommarek, and K.
    Halonen, "A 1.5-V direct digital synthesizer with
    tunable delta-sigma modulator in 0.12um CMOS,"
    IEEE Journal of Solid State Circuits, vol. 40,
    pp. 1978-1982, Sept. 2005.
  • 6 F. Wang, D. Kimball, D. Y. Lie, P. Asbeck,
    and L. E. Larson, "A Monolithic High-Efficiency
    2.4GHz 20dBm SiGe BiCMOS Envelope-Tracking OFDM
    Power Amplifier," IEEE Journal of Solid State
    Circuits, vol. 42, pp. 1271-1281, June 2007.
Write a Comment
User Comments (0)
About PowerShow.com