The 68230 Parallel Interface

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The 68230 Parallel Interface
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Outline

• The 68230 Parallel Interface/Time

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MC68K 68230 Interface
68230
MC68000
CLK
CLK
RESET
RESET
PA
PB
DTACK
DTACK
R/W
R/W
PC
D0-7
D0-7 or D8-15
RS1-5
A1-23
Address Decoder
CS
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Parallel Interface/Timer (PI/T)

• 68230 PI/T
• M68K series Peripheral Controller chip
• 8-bit or 16-bit parallel bus peripherals access
• automatic handling of data exchange across
  parallel bus using handshaking protocols and
  buffering
• Allows programs to perform accurate advanced
  timing operations or wave signal generation

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HANDSHAKING
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HANDSHAKING EXAMPLE(Data receiving)
CONTROLLER to PERIPHERAL I am ready for data
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HANDSHAKING EXAMPLE(Data receiving)
PERIPHERAL to CONTROLLER I have data for you
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HANDSHAKING EXAMPLE(Data receiving)
CONTROLLER to PERIPHERAL I have received your
data and am busy processing it
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HANDSHAKING EXAMPLE(Data receiving)
PERIPHERAL to CONTROLLER I confirm that you
have received the data
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HANDSHAKING EXAMPLE(Data receiving)
CONTROLLER to PERIPHERAL I am ready for data
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BUFFERING

• Buffering temporarily storing data in transit
  between two devices
• Registers in Peripheral Controllers are used to
  buffer peripheral data until the CPU can read it
• Single-buffering data is accomplished using 1
  register
• Double-buffering data is accomplished using 2
  registers

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SINGLE-BUFFERING EXAMPLE

• Peripheral has data

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SINGLE-BUFFERING EXAMPLE

• Data arrives at the Controller and is buffered in
  a register
• While the data is buffered the Peripheral cannot
  transfer further data to the Controller

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SINGLE-BUFFERING EXAMPLE

• Processor (CPU) reads data from the Controller
• The Peripheral may now transfer new data to the
  Controller again

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DOUBLE-BUFFERING EXAMPLE

• Peripheral has data for Controller
• The data is buffered in the Controller

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DOUBLE-BUFFERING EXAMPLE

• While the Controller is waiting for the CPU to
  read the buffered data, more data arrives from
  the Peripheral
• This data can now also be buffered

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68230 Parallel I/O Data Latching/Buffering
Output single-buffered
or double-buffered
Single Buffered
CPU
OUT BUFFER
OUT PORT
Double Buffered
Port A or Port B Data
Non-Latched
IN PORT
IN BUFFER
Double Buffered
Double Buffered
Input Non-latched or
double-buffered
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The Motorola 68230 Parallel Interface Timer
(PI/T)
Port A
Port A Data Register, PADR FF010 Data
Direction Register, PADDR
FF004 Port A Control Register, PACR
FF00C
8 bits wide
Port B
H1-H4
Port B Data Register, PBDR
FF012 Data Direction Register
PBDDR FF006 Port B Control Register,
PBCR FF00E
Port General Control Register
PGCR FF000
8 bits wide
TCR TSR
Port Status Register
PSR FF034
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68230 Block Diagram
port/timer/DMA
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68230 Registers Address Equates

• PIT EQU 0FF000 Base Address of PI/T
• PGCR EQU PIT Address of Port General Ctl
  Register
• PSRR EQU PIT2 Port service request register
• PADDR EQU PIT4 Data direction register A
• PBDDR EQU PIT6 Data direction register B
• PACR EQU PIT0C Port A control register
• PBCR EQU PIT0E Port B control register
• PADR EQU PIT10 Port A data register
• PBDR EQU PIT12 Port B data register
• PSR EQU PIT1A Port status register
• TCR EQU PIT20 Timer control register
• TSR EQU PIT34 Timer status register

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68230 Parallel I/O Input Handshake Timing
Parallel Port A(B) Data
valid
data valid
H1(H3)
data ack ack
(from Peripheral)
ready
ready again
H2(H4)
(from PI/T)
data ack (busy)
Data to CPU (or Buffer)
Data Latched in PIT
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68230 Parallel I/O Output Handshake Timing
CPU Write to port (or buffer)
Parallel Port A(B) Data
valid
ready for more
ready
H1(H3)
data latched
(from Peripheral)
data ready
H2(H4)
latched ack.
(from PI/T)
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68230 PIT Parallel I/O Modes

• Mode 0
• Unidirectional 8-bit, separate PA PB
• Submode 00 - Double Buffered in, Single Buffered
  out
• Submode 01 - Non-Latched in, Double Buffered out
• Submode 1X - Non-Latched in, Single Buffered
  out
• Mode 1
• Unidirectional 16-bit, combined PA
• Submode X0 - Double Buffered (DB) in, Single
  Buffered out
• Submode X1 - Non-latched (NL) in, Double Buffered
  (DB) out
• Mode 2
• Bidirectional 8-bit, separate PA PB
• Port A - NL in, SB out (No handshake,
  unidirectional per bit)
• Port B - DB bidirectional (H1, H2 for output
  H3, H4 for input)
• Mode 3
• Bidirectional 16-bit, combined PA PB
• PA PB - DB bidirectional (H1, H2 for output
  H3, H4 for input)

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Format of Port General Control Register (PGCR)
Example PGCR 00 11
0000 Means Mode 0, Unidirectional
8-bit, separate PA PB Both H34 and H12
handshaking enabled H4-H4 active low
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Format of Port A Control Register (PACR) in Mode
0
Example PACR 00000000
PADDR 00000000 Means Port A
is used as an input port
Submode 0 (Double Buffered input)
H2 Edge-sensitive H2 interrupt
disabled H1 interrupt disabled
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Format of Port B Control Register (PBCR) in Mode
0
Example PBCR 00000000
PBDDR 11111111 Means Port B is
used as an output port Submode
1 (Double Buffered output) H4
Edge-sensitive H4 interrupt disabled
H3 interrupt disabled
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Port Status Register (PSR)

• Reflects activity of the handshake lines

PSR0-PSR3 must be cleared by the program by
writing a 1 onto them Example
Example
MOVE.B 0F,PSR
BTST.B 0,PSR clears bits
PSR0-PSR3 checks the status
of H1
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PI/T Handshaking Input Example

• Continuously check the input handshaking line H1
  of port A, if active a new data byte is read
  from port A and stored in a buffer in memory.
• ORG 1000
• MOVE.B 30,PGCR Initialize PGCR to enable
  handshaking
• MOVE.B 80,PACR I Initialize port A, submode
  1x
• MOVE.B 00, PADDR Set Port A as input
• MOVE.B 0F,PSR Clear PSRs four low status
  bits.
• LEA BUFFER,A0 Load DATA address in A0
• WAIT MOVE.B PSR,D0 Copy PSR into D0
• BTST.B 0,D0 Check if bit 0 of PSR 1
• BEQ WAIT
• MOVE.B PADR,D1 Get a byte from port A
• MOVE.B D1,(A0) Store byte in memory buffer
• MOVE.B 0F,PSR Clear PSRs four low status
  bits.
• BRA WAIT Busy-wait on H1 for more values
• STOP 2700
• ORG 2000
• BUFFER DS.B 1000 Reserve 1000 bytes for buffer
• END

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Printer Port
Error
ACK
Busy
SelectIn
PaperEnd
Init
Select
Strobe
AutoFd
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Printer Pins

• Strobe - Set Low pulse gt0.5 us to send
• D0-D7 Parallel Data
• Ack - Low Pulse 5 uS, after accept
• Busy - High for Busy/Offline/Error
• PaperEnd - High for out of paper
• SelectIn - High for printer selected
• AutoFd - Set Low to autofeed one line
• Error - Low for Error/Offline/PaperEnd
• Init - Set Low pulse gt 50uS to init
• Select - Set Low to select printer

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Printing

• Wait for not Busy (Busy low)
• Set D0-D7 bits
• Pulse Strobe low for 1 µS ? 2 µS
• Some time later, printer will pulse Ack low for
  at least 5 uS
• Printer may lower Busy when it raises Ack at end
  of pulse
• Set other Control outputs or check Status inputs
  as desired

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Printing
no more data
BUSY
send more data
D0-D7
Strobe
Ack
0 µs
0.5 µs
5 µs (min)
0 µs
1 µs ? 2 µs
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Printer Interface Design Exercise

• Get into groups of 6!
• Use a 3-port parallel interface device (e.g.68230
  PI/T).
• Draw the hardware and connections between the
  MC68K CPU, PI/T, and Parallel Printer Cable.
• Use any external hardware (if necessary) to
  generate timing signals.
• Describe the software (i.e. printer driver) that
  you will use. (Take note of signals like PaperEnd
  and Error)