Regular Realization of Symmetric Binary and Ternary Reversible Logic Functions

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Regular Realization of Symmetric Binary and
Ternary Reversible Logic Functions
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Abstract

• We introduce here a new regular structure to
  realize ternary symmetric functions in reversible
  logic
• This idea is very general and applies also to
  binary logic, quaternary logic and any other
  radix
• It should be further investigated if the
  presented approach can be generalized to fuzzy
  logic.
• Based , on my past experience (Singapure paper
  with Edmund) I believe that it cannot be applied
  to classical fuzzy logic, but a (continuous)
  logic similar to fuzzy logic can be defined to
  which it can be applied.
• Because every function is symmetrizable, our
  method allows to realize arbitrary symmetric
  function in a completely regular structure of
  reversible gates with very little waste of
  outputs

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Fredkin Gate

• Fredkin Gate (FG) is the fundamental concept in
  reversible and quantum computing, the base of
  everything.
• It was introduced by Ed Fredkin and Tomasso
  Toffoli in 1982 in Conservative Logic,
  Intern.J.Theor. Phys., 21, pp. 219-253.
• Fredkin Gate has been realized in various ways
• optical
• Cuykendall, R., and McMillin, D,
  Control-Specific Optical Fredkin Circuits,
  Applied Optics, 26, pp. 1959-1963, 1987.
• Shamir, J., Caulfield, H.J., Micelli, W., and
  Seymour, R.J., Optical Computing and the Fredkin
  Gates, Applied Optics, 25, pp. 1604-1607, 1986.
• Picton, P.D., Opto-Electronic Multi-Valued
  Conservative Logic, Int. J. Optical Computing,
  2, pp. 19-29, 1991
• electrical
• De Vos, U.C. Berkeley, Japanese, polish -Lodz, I
  will find
• mechanical (nano-technology)
• Perhaps in Drexler book or papers? We have to
  find
• quantum.
• Smolin, J.A., and DiVincenzo, D.P. Five Two-Bit
  Quantum Gates are sufficient to Implement the
  Quantum Fredkin Gate, Physical Review A, 53, pp.
  2855-2856.

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Multi-Valued Fredkin Gate

• Multi-Valued Fredkin Gate (MVFG) was introduced
  by Picton
• Picton, P.D., Modified Fredkin Gates in Logic
  Design, Microelectronics Journal, 25, pp. 437 -
  441, 1994.
• Picton showed that
• The gates are universal
• T-gates (which are universal) can be build from
  MVFGs.
• Post literals can be build from MVFGs.
• MIN and MAX can be build quite efficiently
• Multi-valued SOP (MAX OF MINs) can be build.
• Thus Picton proved that every MVL circuit can be
  build using his method and his gates.
• However, his design has the following
  disadvantages
• the structure is irregular
• there are many gates
• the delay is long
• I claim that for symmetric functions the method
  below gives much better solutions.
• It is known that every Boolean function can be
  symmetrized and Alan writes an efficient program
  for it. Alan can generalize this program to
  Multi-Valued Logic (MVL).
• I am sure, although it was not formally proven,
  that every multi-valued function can be
  symmetrized.
• I suggest that Xiaoyu will prove it using the
  same method as used by me in paper with
  Malgorzata (VLSI Design, 1998)
• Thus, with the proof and new Alans algorithm,
  the method below will allow to realize arbitrary
  mvl function in a regular structure of reversible
  gates.

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Multi-Valued Fredkin Gate

• Because our structure is programmable, the
  byproduct of this research is that we propose for
  the first time an FPGA for reversible
  multi-valued logic
• In future we should experimentally compare this
  approach to other approaches using software, but
  I believe now it is enough to publish a
  theoretical paper, because what we already have
  is better (from logic synthesis point of view)
  than published by physicists in the journal
  papers above mentioned.
• In future we should have two pieces of software
• Given an arbitrary mvl function F, find its
  symmetric counterpart FS by repeating some
  variables.
• Realize FS in a proposed below regular structure.

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Principles of creating logic synthesis algorithms
for Reversible Logic

• Let us recall that
• In reversible logic wires can cross but in
  Quantum Logic the wires cannot cross.
• In both reversible and Quantum Logic it is not
  possible to have a fanout larger than 1.
• You need a special gate to extend from fanout of
  1 to fanout of 2, high fanout needs introducing
  many such gates which is bad.
• You can use constants in inputs or outputs of
  reversible gates.
• Feedback in gate is not allowed
• Trivial method is to take any known logic
  structure from gates and replace every gate with
  a universal reversible gate. But this generates
  the waste of outputs - a lot of wires that are
  congesting the layout without any use. This is
  very bad for future technologies - remember the
  curse of wiring which will dominate future
  technologies unless cellular-like logic were used
• Quantum Logic is reversible. So, everything that
  we will do here will be useful for Quantum Logic
  as well. I believe these structures are very good
  for QL because they have no wire overlap. So far
  in the papers that I read on QL, they are using
  Fredkin, Toffoli, Margolus, etc binary gates and
  Square-Root-of-Not gate of Feynman that is the
  only gate that cannot be realized in classical
  reversible logic. I believe that we can extend
  principles of symmetry for complete Quantum Logic
  so it will include also Square-Root-of-Not gate
  and many other new gates that I created for QL,
  but because I do not understand quantum
  mechanics, may be these gates are nonsensical
  physically and exist only in theory.

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Principles of creating logic synthesis algorithms
for Reversible Logic

• Smart method of synthesis with reversible gates
  should
• Do not create many outputs of gates
• Re-use these outputs as inputs in other gates
• Apply re-usability properties of these common
  subfunctions - I believe that symmetry introduced
  here is only one of such proporties and we will
  fine more of them
• Be generally applicable
• (I believe) Use regularity and group/field/linear
  algebra properties that are so useful in binary
  logic.

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Multi-valued Fredkin Gate

• MVFG is described by equations
• P A
• Q B
• R C if A lt B else R D
• S D if A lt B else S C

A B C D
P Q R S
gt
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Use Multi-valued Fredkin Gate to create MIN/MAX
gate
Feedback not allowed - so it is a bad gate
Similarly fan-out is not allowed
MIN(A,B)
MAX(A,B)
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Good Use of two Multi-valued Fredkin Gates to
create MIN/MAX gate
MIN(A,B)
MAX(A,B)
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MAX/MIN gate in binary case
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What gates we need to realize every symmetric
function of two binary variables?
All symmetric binary function of polarity 1,1
1
1
1
1
1
1
1 1
NPN Classes for binary
EXOR class of NPN
AND class of NPN
There are two NPN classes of (symmetric)
functions for binary AND and EXOR
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What gates we need to realize every symmetric
function of two binary variables?
1
1
1
1
1
1
1 1
f1 f2 f3 f4
f5 f6
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Property

• Even without ability of realizing any symmetric
  function of two variables one can realize
  arbitrary symmetric function of any number of
  variables
• by building a regular structure from MAX/MIN
  gates and next applying EXORing operations to
  find single-value symmetric coefficients and next
  OR gates to sum them

EXOR level
Regular symmetric structure
OR level
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Every Symmetric Function can be composed of
MIN/MAX gates in case of binary logicExample for
three variables
1
1
1
1
1
1
1 1
C
MAX(A,B,C) (AB)C S 1,2,3(A,B,C)
A
MAX(A,B)
AB
B
C(AB)
MIN(A,B)
AB
S 2,3(A,B,C) (AB) C(AB)
C
0 1
AB
MIN(A,B,C) (AB)C S 3(A,B,C)
1
0
00 01 11 10
2
1
2
3
2
1
Indices of symmetric binary functions of 3
variables
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Every single index Symmetric Function can be
created by EXOR-ing last level gates of the
previous regular expansion structure
1
1
1
1
1
1
1 1
C
S 1,2,3(A,B,C)
A
MAX(A,B)
AB
B
C(AB)
S 1(A,B,C)
MIN(A,B)
AB
S 2,3(A,B,C)
S 3(A,B,C)
S 2(A,B,C)
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Example for four variables
D
MAX(A,B,C,D) ABCD S 1,2,,3,4(A,B,C)
C
MAX(A,B,C) (AB)C S 1,2,3(A,B,C)
A
MAX(A,B)
AB
B
C(AB)
MIN(A,B)
MIN(A,B)
AB
S 2,3(A,B,C) (AB) C(AB)
S,2.3.4(A,B,C,D)
Max/Min gate
MIN(A,B,C) (AB)C S 3(A,B,C)
S 3,4(A,B,C,D)
MIN(A,B,C,D) ABCD S 4(A,B,C,D)
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Example for four variables, EXOR level added
S 1(A,B,C,D)
S 2(A,B,C,D)
S 3(A,B,C,D)
S 4(A,B,C,D)
Now it is obvious that any multi-output function
can be created by OR-ing the outputs of EXOR
level
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Now we generalize for Reversible Logic
S 1(A,B,C,D)
S 2,3,4(A,B,C,D)
S 2(A,B,C,D)
S 3,4(A,B,C,D)
S 3(A,B,C,D)
S 4(A,B,C,D)
Denotes Feynman (controlled NOT) gate
Denotes fan-out gate
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Theorem for Binary Reversible Logic

• Theorem 1 Every positive unate (symmetric )
  function of 2 variables can be realized in 1 gate
• Every positive unate function of 3 variables can
  be realized in 12 gates
• Every positive unate function of 4 variables can
  be realized in 123 gates
• Every positive unate symmetric function of n
  variables can be realized in
• 12.. n-1 n(n-1)/2 MAX/MIN gates

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Theorem for Binary Reversible Logic

• Theorem 2 Every single index totally symmetric
  function of n variables can be realized in
• n(n-1)/2 MAX/MIN gates, n-2 fan-out gates and
  n-1 Feynman gates.

• Theorem 3 Every single-output totally symmetric
  function of n variables can be realized in
  n(n-1)/2 MAX/MIN gates, n-2 fan-out gates, n-1
  Feynman gates and XXX? OR gates.

NOT FINISHED HERE
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Using MIN/MAX gates
A B
Min/Max gate will become now our main building
block
A 0 1 2
A 0 1 2
0 0 0
0 1 2
1,1
0 1 1
1 1 2
1,2
0 1 2
2 2 2
Map of MIN gate
Map of MAX gate
2,2
Symmetric !
Symmetric !
Monotonic!
Monotonic!
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MIN/MAX gates cannot realize every symmetric
function of two variables
A 0 1 2
0,1
0 0 0
0 1 2
A 0 1 2
0 1 2
0 2 1
1,2
1 2 0
Map of Galois Multiplication gate
2 0 1
Symmetric !
Non-Monotonic!
Map of MODSUM Galois Addition gate
Symmetric !
NOT Latin Square!
NOT-Monotonic!
Latin Square!
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What gates we need to realize every symmetric
function of two variables?
1
1
1
A 0 1 2
1
1
1
1 1
All symmetric binary function of polarity 1,1
2,2
1,2
There are two NPN classes of symmetric functions
for binary AND and EXOR
And how it will be for ternary?
1,1
0,2
0,1
0,0