Today

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Lecture 82/12/08

• Today
• Quick look at Lab 3
• Analog-to-Digital Converters
• Quiz 1 (for real) next Tuesday (2/19/08)
• Exam 1 on 2/28/08

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Lab on 2/13/07

• Project will be to investigate performance
  characteristics of an Analog-to-Digital Converter
  (ADC) and a Digital-to-Analog Converter (DAC).

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Why look at ADCs and DACs

• The purpose of this lab is to provide you an
  opportunity to observe, in detail, the
  performance of an Analog-to-Digital Converter and
  a Digital-to-Analog Converter.
• Many of the parameters found in integrated
  devices (such as found on embedded controllers)
  are not observable and just taken for granted.
  You should understand what they are and the
  impact they can have on circuit performance.
  (for example, the processor is running at 20 MHz.
  and conversion time is 40 µsec. - 1000x speed
  difference! How do you handle this?)
• Most embedded devices do not have DAC on-board so
  it is important to understand the interfacing
  requirements of these devices

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Few Items to point out about the lab

• Occasionally, the ADC will not start converting
  when power is applied. You may have to
  momentarily touch the "INTR" pin to ground to
  start the ADC converting.
• Let me stress making some of these measurements
  is not easy because of the limitations of the
  equipment available and in many cases, your
  results will be an approximation at best.
• These devices are sensitive to static and voltage
  levels. For example, if the input waveforms must
  be in the range 0 Vin 5, exceeding this limits
  could damage the device and it may not perform
  properly. Input waveforms must not go negative
  or exceed 5 volts in amplitude, not even for a
  few milliseconds.
• Make sure you understand what you are observing.
  For example, on the output of the DAC you will
  be measuring the output on the DAC at both Vo and
  the filtered output, Vof. The Filter Time
  Constant may have to be adjusted to see the
  effect of the filter more clearly.

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Analog-to-Digital Converters

• There are many different types of
  Analog-to-Digital Converters
• Each offers something in the way of
• Speed
• Cost
• Power Dissipation
• Complexity

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Types of ADCs

• We will first look at the various types
• Investigate the operation of the converters
• And then briefly compare the basic properties

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Types of ADCs

• There are several different types of ADCs
  divided into four categories
• 1) Counter type ADC
• Tracking
• Staircase
• Successive Approximation
• 2) Integrating type
• Single slope
• Dual slope
• Triple slope

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Types of ADCs (continued)

• 3) Flash
• Simultaneous
• Subranging
• 4) Sigma-Delta

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Where ADCs Are Most Effective
Figure 1. ADC architectures cover differing
ranges of sample rate and resolution.
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Now lets look at the various types of ADCs in a
little more detail.Well begin with the counter
type ADCs
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Counter Type ADC

• This type of converter uses some type of counter
  as part of its operation
• Counter type ADCs are sometimes called Digital
  Servo types because a Servo implies Feedback
• Counter type contains the following elements
• Digital-to-Analog Converter
• Some type of counting mechanism
• Comparator
• Clock

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Features Counter Type ADC

• Use a clock to index the counter
• Use DAC to generate analog signal to compare
  against input
• Comparator is used to compare VIN and VDAC where
  VIN is the signal to be digitized.
• The input to the DAC is from the counter.

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One type of Counter type ADC is Digital Ramp or
Staircase
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OperationAs the counter counts up with each
clock pulse, the DAC outputs a slightly higher
(more positive) voltage. This voltage is compared
against the input voltage by the comparator. If
the input voltage is greater than the DAC output,
the comparator's output will be high and the
counter will continue counting normally.
Eventually, though, the DAC output will exceed
the input voltage, causing the comparator's
output to go low. This will cause two things to
happen first, the high-to-low transition of
the comparator's output will cause the shift
register to "load" whatever binary count is being
output by the counter, thus updating the ADC
circuit's output second, the counter will
receive a low signal on the active-low LOAD
input, causing it to reset to 00000000 on the
next clock pulse.
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Staircase

• The effect of this circuit is to produce a DAC
  output that ramps up to whatever level the analog
  input signal is at, output the binary number
  corresponding to that level, and start over
  again.
• Plotted over time, it looks like this

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Typical waveforms
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We can modify this to produce another type.
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Tracking Converter
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OPERATION Another variation on the
counter-DAC-based converter theme is a tracking
device. Instead of a regular "up" counter
driving the DAC, this circuit uses an up/down
counter. The counter is continuously clocked,
and the up/down control line is driven by the
output of the comparator. So, when the analog
input signal exceeds the DAC output, the counter
goes into the "count up" mode. When the DAC
output exceeds the analog input, the counter
switches into the "count down" mode. Either way,
the DAC output always counts in the proper
direction to track the input signal. Notice -
no shift register is needed to buffer the binary
count at the end of a cycle. Since the counter's
output continuously tracks the input (rather than
counting to meet the input and then resetting
back to zero), the binary output is legitimately
updated with every clock pulse. An advantage of
this converter circuit is speed, since the
counter never has to reset. Note the behavior of
this circuit
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Typical Waveforms of Tracking Converter
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Successive Approximation (Block Diagram)

• Figure 4. Successive approximation register (SAR)
  converters use a comparator and a DAC to close in
  on VIN.

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Successive Approximation (Functional Diagram)
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Successive Approximation Operation

• One method of addressing the digital ramp ADC's
  shortcomings is the so-called successive-approxima
  tion ADC.
• The only change in this design is a very special
  counter circuit known as a successive-approximatio
  n register. Instead of counting up in binary
  sequence, this register counts by trying all
  values of bits starting with the most-significant
  bit and finishing at the least-significant bit.
• Throughout the count process, the register
  monitors the comparator's output to see if the
  binary count is less than or greater than the
  analog signal input, adjusting the bit values
  accordingly. The way the register counts is
  identical to the "trial-and-fit" method of
  decimal-to-binary conversion, whereby different
  values of bits are tried from MSB to LSB to get a
  binary number that equals the original decimal
  number.
• The advantage to this counting strategy is much
  faster results the DAC output converges on the
  analog signal input in much larger steps than
  with the 0-to-full count sequence of a regular
  counter.

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Successive Approximation process plotted over
time looks like this
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Successive Approximation Converter Waveforms
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Problems with Counter Type ADCs

• Noise sensitivity
• Taking samples at a high rate can result in the
  digitization of noise
• In some cases the noise will not average out in a
  measurement and several measurements would have
  to be made to average out noise

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Here is 1.5 volt battery noise without any load
on the battery.
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Here is the 1.5 volt battery voltage with motor
noise.
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Here is the battery with motor noise averaged
over time
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Integrating ADC

• Contains many elements similar to other ADCs
• Counter
• Comparator
• Also contains an Integrator
• Serves as a filter to improve noise immunity

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Integrating ADC

• The is the basic idea behind the single-slope,
  referred to as an integrating ADC is as follows
• Instead of using a DAC with a ramped output, we
  use an op-amp circuit configured as an integrator
  to generate a sawtooth waveform which is then
  compared against the analog input by a
  comparator.
• The time it takes for the sawtooth waveform to
  exceed the input signal voltage level is measured
  by means of a digital counter clocked with a
  precise-frequency square wave (usually from a
  crystal oscillator). The basic schematic diagram
  is shown here

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Single Slope ADC
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Integrating ADC
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Typical waveforms of integrating ADC
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Single Slope Integrating ADC

• The single-slope ADC suffers all the
  disadvantages of the digital ramp ADC, with the
  added drawback of calibration drift.
• The accurate correspondence of this ADC's output
  with its input is dependent on the voltage slope
  of the integrator being matched to the counting
  rate of the counter (the clock frequency).
• With the digital ramp ADC, the clock frequency
  had no effect on conversion accuracy, only on
  update time. In this circuit, since the rate of
  integration and the rate of count are independent
  of each other, variation between the two is
  inevitable as it ages, and will result in a loss
  of accuracy.
• The only good thing to say about this circuit is
  that it avoids the use of a DAC, which reduces
  circuit complexity.

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Dual Slope Integrating ADC

• An answer to this calibration drift dilemma is
  found in a design variation called the dual-slope
  converter.
• In the dual-slope converter, an integrator
  circuit is driven positive and negative in
  alternating cycles to ramp down and then up,
  rather than being reset to 0 volts at the end of
  every cycle.
• In one direction of ramping, the integrator is
  driven by the positive analog input signal
  (producing a negative, variable rate of output
  voltage change, or output slope) for a fixed
  amount of time, as measured by a counter with a
  precision frequency clock.
• Then, in the other direction, with a fixed
  reference voltage (producing a fixed rate of
  output voltage change) with time measured by the
  same counter.
• The counter stops counting when the integrator's
  output reaches the same voltage as it was when it
  started the fixed-time portion of the cycle.
• The amount of time it takes for the integrator's
  capacitor to discharge back to its original
  output voltage, as measured by the magnitude
  accrued by the counter, becomes the digital
  output of the ADC circuit.

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Dual Slope Integrating ADC

• The dual-slope method can be thought of
  analogously in terms of a rotary spring such as
  that used in a mechanical clock mechanism.
• Imagine we were building a mechanism to measure
  the rotary speed of a shaft. Thus, shaft speed is
  our "input signal" to be measured by this device.
  The measurement cycle begins with the spring in a
  relaxed state. The spring is then turned, or
  "wound up," by the rotating shaft (input signal)
  for a fixed amount of time. This places the
  spring in a certain amount of tension
  proportional to the shaft speed a greater shaft
  speed corresponds to a faster rate of winding.
  and a greater amount of spring tension
  accumulated over that period of time.
• After that, the spring is uncoupled from the
  shaft and allowed to unwind at a fixed rate, the
  time for it to unwind back to a relaxed state
  measured by a timer device.
• The amount of time it takes for the spring to
  unwind at that fixed rate will be directly
  proportional to the speed at which it was wound
  (input signal magnitude) during the fixed-time
  portion of the cycle.

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DUAL SLOPE ADC

• This technique of analog-to-digital conversion
  escapes the calibration drift problem of the
  single-slope ADC because both the integrator's
  integration coefficient (or "gain") and the
  counter's rate of speed are in effect during the
  entire "winding" and "unwinding" cycle portions.
  
• If the counter's clock speed were to suddenly
  increase, this would shorten the fixed time
  period where the integrator "winds up" (resulting
  in a lesser voltage accumulated by the
  integrator), but it would also mean that it would
  count faster during the period of time when the
  integrator was allowed to "unwind" at a fixed
  rate.
• The proportion that the counter is counting
  faster will be the same proportion as the
  integrator's accumulated voltage is diminished
  from before the clock speed change.
• Thus, the clock speed error would cancel itself
  out and the digital output would be exactly what
  it should be.
• Another important advantage of this method is
  that the input signal becomes averaged as it
  drives the integrator during the fixed-time
  portion of the cycle. Any changes in the analog
  signal during that period of time have a
  cumulative effect on the digital output at the
  end of that cycle.

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Dual Slope ADC

• Other ADC strategies merely "capture" the analog
  signal level at a single point in time every
  cycle.
• If the analog signal is "noisy" (contains
  significant levels of spurious voltage
  spikes/dips), one of the other ADC converter
  technologies may occasionally convert a spike or
  dip because it captures the signal repeatedly at
  a single point in time.
• A dual-slope ADC, on the other hand, averages
  together all the spikes and dips within the
  integration period, thus providing an output with
  greater noise immunity.
• Dual-slope ADCs are used in applications
  demanding high accuracy.

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Here is the 1.5 volt battery voltage with motor
noise.
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Here is the battery with motor noise averaged
over time
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Dual Slope ADC
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Dual Slope ADC

• The Dual Slope Integrating ADC is divided into
  three phases
• Phase I is the Auto zero phase switches are set
  to zero out the integrator capacitor and prepare
  device to integrate signal
• Phase II is the signal integrate phase Signal is
  integrated for a predetermined of clock pulses
• Phas III is the reference integrate phase A
  reference signal is applied to the integrator and
  integrated down while clock pulses are counted

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Dual Slope ADC

• The number of clock cycles required to get to
  zero is proportional to the value of Vin (input
  voltage) averaged over the integration period.

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The Dual Slope Integrating ADC charges a
capacitor for a fixed amount of time, then
discharge while counting output bits.
Dual Slope operation Phase I Phase II
Phase III
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FLASH ADCs- Most high-speed oscilloscopes and
some RF test instruments use flash ADCs because
of their fast digitizing rate, which now reaches
5 Gsamples/s for off-the-shelf devices and 100s
Gsamples/s for proprietary designs. - The
typical flash converter resolves analog voltages
to 8 bits, although sizes are continuing to
increase and some flash converters can resolve
10 bits.
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Flash or Parallel ADC

• Fastest of all ADC
• 100s GHz conversion rates
• Consist of a bank of comparators ( 2n )
• Extensive decoding logic in some cases
• High power dissipation
• No clock necessary
• Major disadvantage - complexity

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Flash ADC
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Typical Waveforms
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Flash ADC circuit configuration
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Flash ADC circuit configuration
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Example 2 bit flash ADC

• Heres an example of the logic in a two bit flash
  converter
• Note if Vref is 8 volts,
• Then resolution is 2 volts
• Transitions occur at 1, 3, and 5 volts.
• Maximum output is 11

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Change the VTC

• Note the Voltage Transfer Characteristic (VTC) of
  the devicee can be easily altered by simply
  changing resistor values, so the switch points
  can be change to create whatever profile you want.

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Sub-ranging Flash ADC

• Combining parallel conversion for moderate number
  of bits (eg. 8) with iteration it is possible to
  strike a compromise that gives
• Better resolution than a full parallel approach
• Less complex structure
• Improved speed over a counter type ADC
• Uses a clock (strobe) to synchronize operations
• Called by different names
• Two step flash ADC
• Subranging ADC

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Sub-ranging Flash ADC

• Operation similar to flash except
• Conversion produces most significant portion of
  output word. This portion is stored and
  converted to analog value with a fast DAC
• Analog result is subtracted from the input, and
  resulting residue is amplified, converted to
  digital value and combined with first part to
  form total output word.

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Sub-ranging Flash ADC
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Delta-Sigma (?S) ADC

• One of the more advanced ADC technologies is the
  so-called delta-sigma, or ?S (using the proper
  Greek letter notation).
• In mathematics and physics, the capital Greek
  letter delta (?) represents difference or change,
  while the capital letter sigma (S) represents
  summation the adding of multiple terms together.
  Sometimes this converter is referred to by the
  same Greek letters in reverse order sigma-delta,
  or S?.
• In a ?S converter, the analog input voltage
  signal is connected to the input of an
  integrator, producing a voltage rate-of-change,
  or slope, at the output corresponding to input
  magnitude.
• This ramping voltage is then compared against
  ground potential (0 volts) by a comparator.
• The comparator acts as a sort of 1-bit ADC,
  producing 1 bit of output ("high" or "low")
  depending on whether the integrator output is
  positive or negative.
• The comparator's output is then latched through a
  D-type flip-flop clocked at a high frequency, and
  fed back to another input channel on the
  integrator, to drive the integrator in the
  direction of a 0 volt output.

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?S CONVERTER
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?S CONVERTER
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?S CONVERTER
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?S CONVERTER
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?S CONVERTER
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?S CONVERTER
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Where ADCs Are Most Effective
Figure 1. ADC architectures cover differing
ranges of sample rate and resolution.
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Sigma-delta ADCsSigma-delta converters , also
called oversampling converters, consist of 2
major blocks modulator and digital filter . The
modulator, whose architecture is similar to that
of a dual-slope ADC, includes an integrator and a
comparator with a feedback loop that contains a
1-bit DAC. The modulator oversamples the input
signal, transforming it to a serial bit stream
with a frequency well above the required sampling
rate. The output filter then converts the bit
stream to a sequence of parallel digital words at
the sampling rate. The delta-sigma converters
perform high-speed, low resolution (1-bit) A/D
conversions, and then remove the resulting
high-level quantization noise by passing the
signal through analog and digital filters
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Features high resolution , high accuracy , low
noise, low cost. Good for applications with a
bandwidth up to 1MHz, such as speech, audio.
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In the schematic above the input analog voltage
drives an integrator, whose output is compared
with a ground voltage level by a comparator.
D-latch controls a switch turning on/off a
reference voltage, they both are composing a
1-bit DAC. As the input voltage increases or
decreases, the comparator turns on and off the
reference voltage, that is subtracted from the
input signal, aiming to maintain zero on the
output of the integrator. The counter C1 keeps
track of clock periods, while counter C2 counts
the number of pulses when the switch is closed.
Suppose the volume of counter C1 is 1000. By the
time it gets the final count, the number in
counter C2 is proportional to the average level
of the input signal during the time of 1000 clock
pulses. Now the name delta-sigma is making a
little more sense delta (the difference) refers
to delta modulation, the principle of coding not
the whole input value, but only the difference
between the current signal sample and the
feedback signal, corresponding to the previous
sample. Obviously, less bits are required to code
only the difference in the amplitudes.
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Sigma (the sum) is because the sum of "deltas" is
counted during the measured interval. In other
words, the input to the quantizer is the integral
of the differences between the input and the
output signals. Technical papers often refer to
sigma-delta converter as over-sampling.
Traditional converter takes a sample of the input
signal and performs a complete conversion with
it. Delta-sigma converter is averaging multiple
samples. The penalty paid for the high
resolution achievable with sigma-delta technology
has always been speed - the hardware has to
operate at the oversampled rate, much larger than
the maximum signal bandwidth, thus demanding
greater complexity of the digital circuitry.
Because of this limitation, these converters have
traditionally been used in high-resolution low
frequency applications (up to 1 MHz, such as
speech, audio, precise voltage and temperature
measurements).