The ESA MUSIC Project Design of DSP HW and Analog TXRX ends

1
The ESA MUSIC ProjectDesign of DSP HW and
Analog TX/RX ends

• Advanced Mobile Satellite Systems Technologies
  presentation days
• ESA/ESTEC 14-15 November 2000

2
Presentation Outline

• The PROTEO Signal Processing Board
• The MUSIC TX/RX Analog Signal Conditioning Units

3
The PROTEO Signal Processing Board
4
The PROTEO Signal Processing Board
5
PROTEO Functional Block Diagram
6
PROTEO Board Main Features Summary

• 12 bit pipelined ADC Converter (BB ADS807) up to
  53MHz sampling.
• 100 Kgates CPLD (Altera Flex EPF10K100A)
• - clock gt100MHz
• - usable gates 90
• - embedded array blocks 12 (ex. RAM, ROM, FIFO
  functions)
• - in-circuit re-configurability via Byte-Blaster
  or JTAG port.
• 66 MIPS 16bit DSP (ST18952).
• On board Memories
• - x CPLD SRAM 256Kx16 SIMM-like Module for
  SRAM 1MB or SDRAM 4MB
• - x DSP SRAM 64Kx16, FLASH 4Mx16.
• Master Clock distribution by Prog. Skew Clock
  Buffer (Cypress CY7B991)
• - selectable skew to 18ns (-12 time units of
  1.5ns).
• Prog. Clock Generator (Cypress ICD2053B) for CPLD
  only
• - clock out 391KHz-90MHz
• - prog. "on the fly" by 2 wire serial interface.
• 2x 12 bit dual DAC converters (Analog Device
  AD5323)
• - high-speed serial interface control logic (up
  to 30 MHz).

7
PROTEO Clocks Distribution
8
MUSIC Breadboard System Overview
9
MUSIC TX - System requirements

• IF Carrier Frequency
  70MHz
• Max Carrier Frequency Uncertainty
  /-100 Hz
• TX Output Power Level -10
  to -30 dBm
• Spurious and Harmonics
  lt40 dBc
• In-Band Ripple
  lt0.1 dB

10
The MUSIC TX/RX Analog IF Front End
11
Up-conversion TX board Block Diagram
12
P1dB Measurements

• P1dB (input) 10 dBm

13
Harmonics and in-band ripple

• Max Outband spurious level -44 dBc

• Isolation LO to Output -65 dB

14
MUSIC RX AGC board Block Diagram
error signal
15
Control loop
IF 70MHz
IF N
1V p-p
to
TP
Signal
Diff.out
MAI
MUSIC Receiver
BALUN
fIF
Noise
Digital Section
B-P
Filter 2
RX SECTION
TP
Loop error
Low-Pass filter
Loop stability!!
16
Loop Bandwidth

• Loop Bandwidth must be limited in order to avoid
  input signal modulation.

• Loop bandwidth fixed 200
  Hz

• Loop gain
  20 dB

17
HP-ADS Simulation Schematic
18
HP-ADS Simulation Input Signal

• Input Signal Average Power Dynamics 20
  dB

• Average Fading rate
  20dB/3ms

19
HP-ADS Simulation Results

• 20 dB Input Power Dynamics
  

• 1 dB Output Power Dynamics
  

20
Conclusions

• Implementation of TX and RX boards
• Testing and measurements has confirmed
  simulations results