Bolstering Faith in GasP Circuits through Formal Verification

1
Bolstering Faith in GasP Circuitsthrough Formal
Verification

• Xiaohua Kong, Radu Negulescu
• McGill University

2
Hierarchy
System-Level
Cell-Level
Unit-level
Switch-Level
3
Levels of Verification
GasP FIFO
System-Level Specification
GasP Cells
Cell-Level Specification
GasP Units
Switch-Level Implementation
Switch-Level Model
4
Outline

• Preliminaries
• Process spaces
• Active-edge specification
• Specification Construction
• Signal-level specification
• System-level specifications
• Hierarchical Verification
• Conclusion

5
Process Spaces
a
c
b
C-element
a
b
c
(b) Waveform
6
Process Spaces (contd)

• Product (Parallel Composition )
• Refinement
• Relabeling
• Semi-hiding

7
Active-Edge Specification
8
Criteria of Good Specifications

• Simple, simple and simple
• Simple so it is easy to construct
• Simple so it is easy to understand
• Simple so it is easy to compute
• Simple so it is easy to reuse

9
Active-edge Specification Construction
R1
R0
Control Unit0
A1
A0
V
10
Specification of GasP Units
Bin?
Bout?
GasP Unit
Bout
Bin
V
11
System-Level Specification
Cell0
Cell1
Cell2
Cell3
Cell4
Cell5
Cell6
Cell7
Cell8
Cell9
Cell10
Cell11
Cell12
Cell13
Cell14
Cell15
12
System-Level Specification (Contd)

• Capacity of 16 data items
• 0 V0 V19 16

r0, rr0
r0, rr0
r0, rr0
r0, rr0
0
1
2
16

g
e
e
e
r16, rr16
r16, rr16
r16, rr16
r16, rr16
13
System-Level Specification (Contd)

• Data Movement on top row

14
Top Row Rule Specification
V0
V1
Cell0
V4
15
Switch-level Verification
GasP FIFO
System-Level Specification
GasP Cells
Cell-Level Specification
16
GasP Unit Implementation
17
Switch-Level Modeling
d
c
Node with Keeper
Node with Keeper
cout
y
NandOut
y
rout
sout
s
r
NodeBin
NodeBout
BinDn
BoutUp
BoutDn
BinUp
Nand Node
NandUp
t
Bout
a
and
a
Bin
NandDn
aout
Control Unit1
Control Unit0
18
Node Models
r
NandUp
NandDn
g
e
r
NandUp
NandDn
NandOut
NandOut
e
g
NandUp
NandDn
NandUp
NandDn
r
NandUp, NandDn, NandOut
19
Cell-level Verification
GasP FIFO
System-Level Specification
Switch-Level Implementation
Switch-Level Model
20
Cell-Level Verification
v1
r0_Bout
r1_Bin
r1
a0
r1
r0
r1rr1_Bin
b0
E0
F0
r0_Bout-
r0
rr1
rr0
rr1
d1
rr0_Bout-
Selection r0rr0
rr0
Selection r1rr1
d1_Bin
F1
E1
d1
SpecCell1 ? r0rr0 ? r1rr1 ? d1
21
Cell-level Verification
Signal-Level Specification
GasP Units
Switch-Level Implementation
Switch-Level Model
22
Experimental Results
Table 1. Relative timing constraints for the
linear GasP unit.

Level Constraint
Switch-level 9
Cell-level 4
System-Level (FIFO) 0

1 A keeper is used at Sun to guard against this
noise sensitivity.
23
Square FIFO Ebergen 01
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Top Row Simplified
1
V0
V2
V1
V3
V7
V5
V6
V4
d8
d5
d6
d7
d12
d9
d10
d11
rr13
rr14
rr15
rr16
r14
r15
r16
25
Where is Stubborn Donkey ?
V0
V2
V1
V3
V7
V5
V6
V4
12
d8
d5
d6
d7
8
d12
d9
d10
d11
rr13
rr14
rr15
rr16
1
2
3
4
r14
r15
r16
26
Conclusion

• Specification and Verification of GasP
• Modularity of GasP leads to simple specs
• Simple system level specifications
• Simple active-edge unit specs