VIRAM-1 Verification

1
VIRAM-1 Verification

• Retreat Winter 2001
• Sam Williams

2
Current Debug / Verification Efforts

• Current
• m5kcfpu program simulation on RTL
• m5kcvuxbardram program simulation on RTL
• AU corner cases random values
• on VERILOG netlist
• To Do
• Entire VIRAM-1 program simulation on RTL
• (m5kcvufpuxbardram)
• Vector Register File only a few cases have
  been
• (layout) spiced.

3
Verify script

• Command line args include mode, and switches for
  disabling state initialization, method for
  init/test, run from on/off chip, turn of TLB,
  etc
• Implemented a trace comparator capable of
  handling out of order commit, and partial
  execution
• few issues need to be hammered out for vu trace
  generation
• Tests can fail for self-check (software),
  unexpected exceptions, simulator failure, traces
  not consistent, etc
• Since there are currently two different
  processors being verified, each had to have its
  own verify script and random test generator.

4
Progress
Entire VIRAM-1 Testsuite
vsim
ISA
XCs
Arith. ?Kernels
TLB ?Kernels
random
compiled
m5kc
MIPS Testsuite
Testsuite on Synthesized
FPU Subset of VIRAM-1 Testsuite MIPS FPU
Testsuite
m5kcfpu
ISA
XCs
Arith. ?Kernels
random
compiled
Testsuite on Synthesized
MIPS
Vector Subset of VIRAM-1 Testsuite
m5kcvu xbardram
ISA
XCs
Arith. ?Kernels
TLB ?Kernels
random
compiled
Testsuite on Synthesized
VIRAM-1 (superset of above)
Entire VIRAM-1 Testsuite
Testsuite on Synthesized

• MIPS testsuite is about 1700 test-mode
  combinations lt100 FP tests-mode combinations
  that are valid for the VIRAM-1 FPU
• Additionally, entire VIRAM-1 testsuite has about
  2200 tests, each of which can be run in 200 modes
  (only 1 mode has been run). Each mode is 24M
  instructions, and 4M lines of asm code
• Vector unit currently passes about 1800 tests
  (only the ISA sub suite)
• There are about 200 exception tests for both
  coprocessors
• Kernel tests are long, but there are only about
  100 of them
• Tests are continually being written, so that they
  are ready once the RTL can run them

5
Test File Format Retrospective

• init/test functions arent written by the test
  writter, this allowed them to be switched as
  needed. e.g. when vld/vst werent working,
  vector register init/test was handled via
  vins/vext. The test was identical, all that
  changed was a command line option.
• xbar had a bug in it which prevented any access
  to DRAM (from m5kc or vu). Another command line
  allowed running tests from off chip memory, and
  forced application of the previous option
• Test format allows for easy modification to
  reduce simulation time in a debug cycle.
• Difficult to apply ISA changes to the entire test
  suite. e.g. half as many registers, changes in
  functionality for instructions, narrow element
  ordering, etc

INIT vr0 half 0x7fff 0x0001 0xffff 0x7fff
0x0001 0xffff 0x7fff 0x0001 0xffff vr1 half
0x7fff 0x7fff 0x7fff 0x0001 0x0001 0x0001 0xffff
0xffff 0xffff CODE li a0,1 vcset
a0,vpw li a0,9 vcset a0,vl
vfclr vf8 vfset vfmask0 vadd.vv
vr2,vr1,vr0 vfor.sv vf16,vs0,vf8
END TEST vr2 half 0xfffe 0x8000 0x7ffe
0x8000 0x0002 0x0000 0x7ffe 0x0000 0xfffe vf16
hex1 d0000000000000000000000000000000
6
Bug Trends

• xbar/DRAM/SysAD timing and arbitration problems
• VERILOG could use extensions for handling control
  logic for multiple lanes instead of copying and
  modifying code, which led to many typos
• Major mistake in xbar functionality had to be
  fixed with major memory pipeline change.
• A few chaining errors so far
• Tests which had hand coded versions of boot code
  were not kept syncd with master version (e.g.
  some regs had to be initialized, and were in
  master version, but not in the handful of tests
  which had their own version)
• ISA docs were not kept in sync with RTL, as a
  result many tests which look correct failed on
  RTL. (vector processing instructions, lack of
  interlocks)
• FP execution unit as it was shipped to us had
  many flaws with respect to exceptions and NaNs
  fixed to make it IEEE compliant
• FP reorder buffer / CDB problems missing results
• cop0 hazards initially werent reported by vsim,
  and caused hard fails on RTL
• Instruction Encoding some instructions were
  encoded differently in the RTL than what had been
  used by the assembler / software simulator

7
VIRAM-1 Board

• Daughter card (modified m5kc core card) has DIMM,
  VIRAM-1, and chipset (which maps SysAD?PCI,SDRAM)
• Yamon software can be used to directly download
  and run programs to daughter card via ethernet or
  serial.
• An m5kc based core card will allow us to run thru
  the methodology before receiving parts.
• Atlas board has PCI, compact PCI, SCSI, Parallel,
  Ethernet, KB/Mouse, USB, Serial devices.
• Will allow for creation of VIRAM-1 workstation
• For OS support, we would have to modify an
  unsupported MIPS Linux port. The vector unit can
  only touch on chip memory.

8
Still Left To Do

• FPU RTL almost done, needs a little more work.
• VU RTL verification needs to be completed, only
  done with ISA
• Integrate everything together for VIRAM-1 RTL
  model
• Include real versions of AU, xbar, VRF
• Iterate over timing driven layout, to ensure
  nothing is broken
• Board/daughter card checks
• Linux/MIPS port to Linux/VIRAM-1