Using NanoSim for Circuit Simulation and Power Estimation

1
Using NanoSim for Circuit Simulation and Power
Estimation

• ECE-652
• Spring 2005
• Darren Ellis

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Introduction

• Nanosim is an advanced transistor-level circuit
  simulation tool
• Design Verification
• Analog
• Digital
• Mixed Signal

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Key Benefits

• Fast Simulation Speed
• Can be several orders of magnitude faster than
  SPICE
• Intelligent partitioning and synchronization of
  design parallelizes computations

4
Key Benefits

• Integration with parasitic extraction tools
• Supports all major SPICE netlists and model
  formats
• GUI or command line interface

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Key Benefits

• Flexible
• Can trade off accuracy for performance in the
  simulation
• Capacity for simulating large SoC and Memory
  designs (109 element designs!)

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Key Benefits

• Provides high accuracy for designs at 90
  nanometer and below
• Built in timing and power diagnostic capabilities

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NanoSim Supports the Following
Netlist Input SPICE, Verilog, EDIF, LSIM,
SPF, SPEF Stimulus .vec, Verilog HDL
testbenches (VCS required) Models BJTs,
BSIM3.x, BSIM 4.x MM905, JFET, MESFET, HVMOS,
SiGe VBIC, SOI, etc.
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NanoSim Supports the Following

• Use of pre-characterized technology files for
  faster run times
• Output .out, turboWave .fsdb and API for custom
  output into other display tools.

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Using NanoSim

• Manuals almost 1500 pages for your reading
  pleasure
• Command Line interface or run through GUI
• Homework will focus on Command line Interface

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NanoSim Methodology
Spice
Stimulus
Parasitics
NanoSim
Power
Waveform
Timing
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Homework

• Part A
• Explores the simulation capability of NanoSim
• Use your 8-bit adder from last semester to
  perform some simulations
• Use Synopsys CosmosScope for viewing waveforms

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Homework

• Part B
• Use your 8-bit adder from last semester to
  perform power simulation with a given set of
  inputs
• Stimulus is generated within .SPI File (PWL)
• Email your results to Darren for this part link
  on homework webpage

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Homework

• Part C
• Perform power simulation on 16-bit adder
• Use external Stimulus file (.VEC)
• 1024 test vectors applied to DUT

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References

• http//www-ece.engr.utk.edu/ece/balash-thesis.pdf
• http//www.synopsys.com/products/mixedsignal/nanos
  im/nanosim.html
• http//www.synopsys.com/products/mixedsignal/nanos
  im_wp.pdf
• http//www.synopsys.com/products/mixedsignal/nanos
  im/nanosim_ds.pdf
• Nanosim User Guide

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The End!

• Thank You!