Tendncies

1
Tendències
Joan Figueras
2
Transistor Integration
1 Giga Transistors
1000
Pentium 4 proc
100
10
Million
Transistors
1
386
Pentium proc
0.1
8086
0.01
8080
0.001
1970
1980
1990
2000
2010
2020
3
ITRS Roadmap 2005 vs Moores law

• Product Functions/Chip and Industry are on the
  average Moores Law Trends

4
Squeezing Costs of Computing Cores Example
ARM 9 180 nm 11.8 mm2
5
Application rush
3D gaming
1TOPS/W
3D TV
3D ambient interaction
Structured decoding
Ubiquitous navigation
3D projected display
Autonomous driving
HMI by motion Gesture detection
Structured encoding
100GOPS/W
Expression recognition
Gbit radio
Collision avoidance
Adaptive route
H264 encoding
Language
dictation
Emotion recognition
Gesture recognition
UWB
Sign recognition
A/V streaming
5 GOPS/W
Image recognition
802.11n
Si Xray
Mobile Base-band
H264 decoding
Auto personalization
Fully recognition (security)
2005
2007
2009
2011
2013
2015
Year of Introduction
6
Power Trend for microprocessors

• Power density in Intels microprocessors

Source INTEL Corp.
7
Electronic Technology Today CMOS Convergence

• CMOS technology dominates in modern ICs.

CMOS
8
CMOS at Core of Chip Making

• Silicon will continue to be the leading-edge
  semiconductor technology for the next decade
  source ITRS, STM, IFX.

CHANNEL Length
Room for improvement 26X
GATE delay
Room for improvement 25X
Room for improvement 6X
TRANSISTOR DENSITY
9
VDD (no more) Scaling is Increasing the Power
Crisis
5V plateau
Regular Decrease in 10 years From 5V to 1.2V (x
0.7 per node)
1V plateau ???
1.2V plateau
1.1V
120
90
65
32
250
350
700
45
500
180
10
Thermal Management Challenge
BGA Normalized cost vs. thermal enhancement
Ceramic
max cost
Metal
min cost
Organic
0
1
2
3
4
5
6
Source STM Corporate Packaging
Normalized cost

• BGA package rough (Cost-performance
  High-performance)
• max power density 5060 W/cm2
• Cost per pin 0.251.1 /pin ( 90 pins/cm2)
• Max pincount 5002500

Source STMicroelectronics
11
CAD per a disseny VLSI
DesignDescription(C,SystemC, VHDL, Verilog)
Front-End
HW/SW Partitioning
Architectural Exploration and (IP) Block Selection
Block Design/Synthesis
Block Integration and Communication Design
RTL Planning/Optimization(DataPath, Memory,
Buses,Clock, Power Distribution,Test Structures)
Physical Synthesis
Back-End