LAB 3 Presentation

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LAB 3 - Presentation

• VLSI-I (EE360R/EE382M)
• Spring 2007

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Overview

• RTL level system design using Verilog (Behavioral
  modeling) to design
• Part A Synchronous Serial Port (SSP)
• Part B Integration of SSP with ARM processor
  using a SoC bus interface called WISHBONE
• Tools
• Simulation
• VCS Verilog simulation tool
• VirSim GUI to control simulation and view
  waveforms
• Synthesis
• Design Vision Logic Synthesis

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VLSI Lab Overview

• Verilog
• Hardware Description Language (HDL)
• Behavioral Description
• Structural Description
• Synthesizable code

RTL level
Vcs/ virsim
lab3
Design Analyzer (Synthesis tool)
Gate level
Virtuoso editor
lab2
SE (APR tool)
Tr. level
lab1
Virtuoso editor
Layout
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Verilog Level of Abstraction

• Behavioral Level
• Procedural code, similar to C
• Dataflow Level
• Specific transfer of data between registers
• Structural (gate, switch) Level
• A one-to-one correspondence between the logic
  circuit diagram and the Verilog description

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Some Definitions

• RTL (Register Transfer Level)
• Typically a combination of behavioral and
  dataflow constructs and is acceptable to logic
  synthesis tool
• Logic synthesis
• The process of converting a high-level
  description of the design into an optimized
  gate-level representation

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Lab3 System Overview (what is given to you)
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Lab3 System Overview (what you should do)
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Lab3A SSP Design

• SSP Perform
• Parallel-to-serial conversion on data received
  from a processor (i.e., wishbone bus interface)
• Serial-to-parallel conversion on data received
  from a peripheral device
• Your design
• Your SSP provides buffering capability on both
  the TX and RX logic using FIFOs to allow up to
  four 8-bit words to be stored in independently in
  both TX and RX module

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Lab3A SSP Block Diagram
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Lab3A SSP Specifications

• Transmit FIFO(TxFIFO)/ Receive FIFO(RxFIFO)
• 8-bit wide, 4-location deep FIFO memory buffer
• Only valid data need to be buffered
• If FIFO is full, generate SSPTXINTR/SSPRXINTR
  interrupt signal and refuse to accept any
  additional data
• Transmit and Receive Logic
• TX Logic
• read from TxFIFO and perform parallel-to-serial
  conversion
• Send the serial data synchronously
• RX Logic
• perform serial-to-parallel conversion on the
  incoming data synchronously
• Send data into RxFIFO

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Lab3A Port Descriptions

• Name your top module as ssp
• You should use the exact names shown below
• SSP module port description
• Input port PCLK, CLEAR_B, PSEL, PWRITE,
  PWDATA70, SSPCLKIN, SSPFSSIN, SSPRXD
• Output port PRDATA70, SSPOE_B, SSPTXD,
  SSPCLKOUT, SSPFSSOUT, SSPTXINTR, SSPRXINTR

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Lab3A Signal Description

• Please refer to the lab website for details
• Signal descriptions
• CLEAR_B Low active clear signal
• SSPCLKIN(RxLogic), SSPCLKOUT(TxLogic)
• Synchronization clock for data transfer
• 2 times slower than PCLK (clock for SSP)
• PSEL Chip select signal for SSP
• PWRITE High Write to SSP, Low Read from SSP
• SSPFSSIN(RxLogic), SSPFSSOUT(TxLogic)
• Indicate starting of data transfer
• SSPOE_B Low active output enable signal,
  indicating when SSPTXD is valid (Used only for
  transmission)
• Assume perfect synchronization between SSPCLKIN
  and SSPCLKOUT - testing is done with external
  loop back
• Dataflow (Written by the processor) ? SSP TxFIFO
  ? SSPTXD ? SSPRXD ? SSP RxFIFO ? (Read by the
  processor)

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Lab3A Timing Diagram (single transfer)
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Lab3A Timing Diagram (continuous transfer)
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Lab3A - Procedures

• Design a module (module.v ssp.v in lab3A)
• Make a testbench file (test_module.v
  ssp_test2.v in lab3A)
• Make a makefile (make_module i.e., ssp_test2.v
  ssp.v)
• Simple list of verilog files to compile
• Run simulation
• Command vcs RI Mupdate f make_module

test_module.v
provide input data/signals
module.v
Observe output data/signals
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Lab3A Logic Synthesis

• Regularly synthesize your code by reading in your
  design to make sure your design is synthesizable

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Lab3B WISHBONE SoC interconnection interface

• Objective
• To design WISHBONE bus interface module to
  integrate heterogeneous modules

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Lab3B Concepts

• SoC (System On Chip)
• Integrate electronic systems (chips) into a
  single chip
• Takes an enormous amount of time and effort to
  design chips from scratch
• Desire to make new products quickly
• Solution
• Reuse parts from the previous designs
• Make use of parts designed by third party vendors
• Part is called IP (Intellectual Property) core
• All problems solved?
• Not yet! Integrating heterogeneous parts into a
  single chip cause bus controlling problem because
  each part is designed with different criteria ?
  Inconsistency between input/output port
  specifications
• Solution Bus interface architecture i.e.,
  WISHBONE SoC interconnection architecture
  suggested by Silicore Co.

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Lab3B Module Descriptions

• ARM processor (Given)
• A master core of your system
• Memory module (Given)
• Simple memory block used as an instruction memory
• Synchronous Serial Port (Designed in Lab3A)
• Slave core of your system
• WISHBONE (Need to design in Lab3B)
• WISHBONE master communicate with the ARM core
• WISHBONE slave communicate with the SSP and
  memory module

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Lab3B WISHBONE

• Master
• When the ARM core gets the data transfer
  activities, WISHBONE master has to transfer the
  data from/to the WISHBONE slave
• Slave
• Transfer the data to/from the memory of SSP
  according to request from the ARM core, and then
  report the result of the transfer to the WISHBONE
  master
• Should be done with WISHBONEs timing
  specifications

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Lab3B WISHBONE (Cont)

• Instruction Read
• When ARM accesses h00000000 h000FFFF
• Generate memory access signals
• Deliver instructions from memory to ARM
• Mem ? Slave ? Master ? ARM
• Path Read signal (ARM) ? master ? slave ? memory
  ? data from memory ? slave ? master ? ARM
  (instruction transferred to ARM)
• Data Read from SSP
• When ARM access h0010001
• Generate SSP access signals
• Deliver data from SSP (RxFIFO) to ARM
• SSP ? Slave ? Master ? ARM
• Path Read signal (ARM) ? master ? slave ? SSP ?
  data from SSP ? slave ? master ? ARM (data
  transferred to ARM)

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Lab3B WISHBONE (Cont)

• Data Write to SSP
• When ARM access h0010000
• Generate SSP access signals
• Deliver data from ARM to SSP (TxFIFO)
• ARM ? Master ? Slave ? SSP
• Path Read signal and data (from ARM) ? master ?
  slave ? SSP (data written to SSP)
• Interrupt Handling
• Stop ARM by holding phi1 and phi2
• E.g., SSP Overflow Interrupt
• SSP ? Slave ? Master (holds clocks)

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Lab3B Simulation

• Write your own assembly test program using ARM
  instructions
• Read ARM manual given to you
• Compile the assembly code and save it to
  /image/mem.dat (?actual memory image)
• asm_arm my_assembly_code gt mem.data
• Template mem.data can be found in Lab3 website
  you may choose to create your own
• Run VCS/VirSim
• make_file for TOP module

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Lab3B Example of Simulation Results(Screen
shot)

• MOV R2, 000001111010 ? e3a0207a
• MOV R0, 000000000000 ? e3a00000
• MOV R6, 000000010000 ? e3a06010

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Lab3B Example of Simulation Results(Screen
shot)

• Data Write to SSP (h0010000)
• MOV R0, 000000000000
• MOV R6, 000000010000
• MOV R7, 000000000001
• ADD R8, R0, R7 LSL R6
• STR R2, R8

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Lab3B Synthesis (New Modules Only)

• Use Design Vision
• Code should be synthesizable
• i.e., readable from Design Vision without error
  messages
• Library had no flips with async reset use
  synchronous reset if you need to clear flop
  contents
• Observe area/timing tradeoff
• First, run without constraint (initial run)
• You can get initial area and initial arrival time
  at this stage
• Run with area optimization option with smaller
  area than initial run
• Run with timing optimization option with smaller
  clock period than initial arrive time

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LAB 3 DEMO
Thank you!